Patents
Sitemap › H01 - Basic electric elements › H01L - Semiconductor devices; Electric solid state devices not otherwise provided for › H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
Patents for H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof (658,974)
10/2001
10/23/2001US6307260 Microelectronic assembly fabrication with terminal formation from a conductive layer
10/23/2001US6307256 Semiconductor package with a stacked chip on a leadframe
10/23/2001US6307254 Technique for attaching die to leads
10/23/2001US6307251 Semiconductor device having capacitance element and method of producing the same
10/23/2001US6307247 Monolithic low dielectric constant platform for passive components and method
10/23/2001US6307246 Semiconductor resurf devices formed by oblique trench implantation
10/23/2001US6307245 Semiconductor device
10/23/2001US6307240 Pulsed etching manufacturing method and system
10/23/2001US6307239 CMOS sense structure having silicon dioxide outer ring around sense region
10/23/2001US6307236 Semiconductor integrated circuit device
10/23/2001US6307235 Another technique for gated lateral bipolar transistors
10/23/2001US6307234 Complementary MOS semiconductor device
10/23/2001US6307233 Electrically isolated double gated transistor
10/23/2001US6307232 Semiconductor device having lateral high breakdown voltage element
10/23/2001US6307231 Method of fabricating semiconductor device
10/23/2001US6307230 Transistor having an improved sidewall gate structure and method of construction
10/23/2001US6307229 Nonvolatile semiconductor memory device structure with superimposed bit lines and short-circuit metal strips
10/23/2001US6307228 Semiconductor device with perovskite capacitor and its manufacture method
10/23/2001US6307227 Semiconductor device and manufacturing method thereof
10/23/2001US6307226 Contact openings to electronic components having recessed sidewall structures
10/23/2001US6307225 Insulating material, substrate covered with an insulating film, method of producing the same, and thin-film device
10/23/2001US6307224 Double diffused mosfet
10/23/2001US6307222 Power/ground metallization routing in a semiconductor device
10/23/2001US6307221 InxGa1-xP etch stop layer for double recess pseudomorphic high electron mobility transistor structures
10/23/2001US6307220 Semiconductor device
10/23/2001US6307217 Semiconductor memory device having driver and load MISFETs and capacitor elements
10/23/2001US6307216 Thin film transistor panels for liquid crystal displays
10/23/2001US6307215 TFT array with photo-imageable insulating layer over address lines
10/23/2001US6307214 Semiconductor thin film and semiconductor device
10/23/2001US6307211 Semiconductor alignment tool
10/23/2001US6307209 Pattern-transfer method and apparatus
10/23/2001US6307184 Thermal processing chamber for heating and cooling wafer-like objects
10/23/2001US6307161 Partially-overcoated elongate contact structures
10/23/2001US6307160 High-strength solder interconnect for copper/electroless nickel/immersion gold metallization solder pad and method
10/23/2001US6307159 Bump structure and method for making the same
10/23/2001US6307001 Amine, ether or sulfide groups with vinyl ethers
10/23/2001US6306807 Post plasma ashing mixture includes ethanolamine, water and catechol
10/23/2001US6306788 Translucent alumina sintered body and production thereof
10/23/2001US6306780 Method for making a photoresist layer having increased resistance to blistering, peeling, lifting, or reticulation
10/23/2001US6306779 Method for nano-structuring amorphous carbon layers
10/23/2001US6306778 Substrate processing method
10/23/2001US6306777 Flash memory having a treatment layer disposed between an interpoly dielectric structure and method of forming
10/23/2001US6306776 Catalytic breakdown of reactant gases in chemical vapor deposition
10/23/2001US6306775 Methods of selectively etching polysilicon relative to at least one of deposited oxide, thermally grown oxide and nitride, and methods of selectively etching polysilicon relative to BPSG
10/23/2001US6306774 Method of forming a wordline
10/23/2001US6306773 Method of producing a semiconductor device of SiC
10/23/2001US6306772 Deep trench bottle-shaped etching using Cl2 gas
10/23/2001US6306771 Process for preventing the formation of ring defects
10/23/2001US6306770 Method and apparatus for plasma etching
10/23/2001US6306769 Use of dual patterning masks for printing holes of small dimensions
10/23/2001US6306768 Method for planarizing microelectronic substrates having apertures
10/23/2001US6306767 Self-aligned etching method for forming high areal density patterned microelectronic structures
10/23/2001US6306766 Method of forming a crystalline phase material, electrically conductive line and refractory metal silicide
10/23/2001US6306765 Method for the formation of thin films for use as a semiconductor device
10/23/2001US6306764 Batch type heat-treating method
10/23/2001US6306763 Enhanced salicidation technique
10/23/2001US6306762 Forming aluminum alloy, forming metal layer in direct contact with aluminum alloy, forming metal nitride; conductively coupled so conduction continues even if alloy layer becomes non-conducting
10/23/2001US6306761 Method of manufacturing semiconductor device
10/23/2001US6306760 Method of forming a self-aligned contact hole on a semiconductor wafer
10/23/2001US6306759 Method for forming self-aligned contact with liner
10/23/2001US6306758 Multipurpose graded silicon oxynitride cap layer
10/23/2001US6306757 Method for forming a multilevel interconnect
10/23/2001US6306756 Method for production of semiconductor device
10/23/2001US6306755 Method for endpoint detection during dry etch of submicron features in a semiconductor device
10/23/2001US6306754 Method for forming wiring with extremely low parasitic capacitance
10/23/2001US6306753 Feasible, gas-dielectric interconnect process
10/23/2001US6306752 Connection component and method of making same
10/23/2001US6306751 Apparatus and method for improving ball joints in semiconductor packages
10/23/2001US6306750 Bonding pad structure to prevent inter-metal dielectric cracking and to improve bondability
10/23/2001US6306748 Bump scrub after plating
10/23/2001US6306743 Method for forming a gate electrode on a semiconductor substrate
10/23/2001US6306742 Method for forming a high dielectric constant insulator in the fabrication of an integrated circuit
10/23/2001US6306741 Method of patterning gate electrodes with high K gate dielectrics
10/23/2001US6306738 Modulation of gate polysilicon doping profile by sidewall implantation
10/23/2001US6306737 Method to reduce source-line resistance in flash memory with sti
10/23/2001US6306736 Process for forming shaped group III-V semiconductor nanocrystals, and product formed using process
10/23/2001US6306735 Method for producing a semiconductor wafer
10/23/2001US6306734 Method and apparatus for growing oriented whisker arrays
10/23/2001US6306733 Ideal oxygen precipitating epitaxial silicon wafers and oxygen out-diffusion-less process therefor
10/23/2001US6306732 Method and apparatus for simultaneously improving the electromigration reliability and resistance of damascene vias using a controlled diffusivity barrier
10/23/2001US6306731 Semiconductor device and method for fabricating the same
10/23/2001US6306730 Method of fabricating an SOI wafer and SOI wafer fabricated by the method
10/23/2001US6306729 Semiconductor article and method of manufacturing the same
10/23/2001US6306728 Stable high voltage semiconductor device structure
10/23/2001US6306727 Advanced isolation process for large memory arrays
10/23/2001US6306726 Method of forming field oxide
10/23/2001US6306725 In-situ liner for isolation trench side walls and method
10/23/2001US6306724 Method of forming a trench isolation structure in a stack trench capacitor fabrication process
10/23/2001US6306723 Method to form shallow trench isolations without a chemical mechanical polish
10/23/2001US6306722 Method for fabricating shallow trench isolation structure
10/23/2001US6306721 Method of forming salicided poly to metal capacitor
10/23/2001US6306720 Method for forming capacitor of mixed-mode device
10/23/2001US6306719 Method for manufacturing a semiconductor device
10/23/2001US6306718 Method of making polysilicon resistor having adjustable temperature coefficients
10/23/2001US6306717 Method of manufacturing an avalanche diode with an adjustable threshold
10/23/2001US6306715 Method to form smaller channel with CMOS device by isotropic etching of the gate materials
10/23/2001US6306714 Method to form an elevated S/D CMOS device by contacting S/D through the contact of oxide
10/23/2001US6306713 Method for forming self-aligned contacts and local interconnects for salicided gates using a secondary spacer
10/23/2001US6306712 Sidewall process and method of implantation for improved CMOS with benefit of low CGD, improved doping profiles, and insensitivity to chemical processing
10/23/2001US6306710 Fabrication of a gate structures having a longer length toward the top for formation of a rectangular shaped spacer
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