Patents
Patents for H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof (658,974)
11/2001
11/01/2001WO2001082344A2 Method of patterning lead zirconium titanate and barium strontium titanate
11/01/2001WO2001082343A2 Heat management in wafer processing equipment using thermoelectric device
11/01/2001WO2001082342A1 Gas assisted rapid thermal annealing
11/01/2001WO2001082341A1 Thermal processing system and thermal processing method
11/01/2001WO2001082340A1 Method and device for treating a substrate
11/01/2001WO2001082339A2 Method and device for the wet-chemical removal of layers and for cleaning plate-shaped individual substrates
11/01/2001WO2001082338A1 Method and device for transporting wafers
11/01/2001WO2001082337A1 Device and method for treating semiconductor wafers
11/01/2001WO2001082335A2 Real-time evaluation of stress fields and properties in line features formed on substrates
11/01/2001WO2001082334A2 Semiconductor handler for rapid testing
11/01/2001WO2001082333A2 Homogeneous gate oxide thickness for vertical transistor structures
11/01/2001WO2001082329A2 Highly efficient compact capacitance coupled plasma reactor/generator and method
11/01/2001WO2001082328A2 Magnetic barrier for plasma in chamber exhaust
11/01/2001WO2001082275A1 Display panel substrate, method for producing the same, thin-film forming apparatus used therefor
11/01/2001WO2001082084A1 Enhanced programmable core model with integrated graphical debugging functionality
11/01/2001WO2001082055A1 Reticle management system
11/01/2001WO2001082019A1 Method and device for conditioning atmosphere in a process chamber
11/01/2001WO2001082002A1 Resist stripper composition
11/01/2001WO2001082000A1 Optical reduction system with elimination of reticle diffraction induced bias
11/01/2001WO2001081977A2 Optical reduction system with control of illumination polarization
11/01/2001WO2001081976A2 Apparatus, system, and method for active compensation of aberrations in an optical system
11/01/2001WO2001081970A2 Apparatus, system, and method for precision positioning and alignment of a lens in an optical system
11/01/2001WO2001081903A1 Holder mechanism
11/01/2001WO2001081902A1 Apparatus and methods for detecting killer particles during chemical mechanical polishing
11/01/2001WO2001081856A2 Technique for determining curvatures of embedded line features on substrates
11/01/2001WO2001081780A1 Magnetic bearing and magnetic levitation apparatus
11/01/2001WO2001081651A1 Method and system for pumping semiconductor equipment from transfer chambers
11/01/2001WO2001081650A1 Sputter target, barrier film and electronic component
11/01/2001WO2001081496A1 Polishing compound and method for preparation thereof, and polishing method
11/01/2001WO2001081490A2 Slurries of abrasive inorganic oxide particles and method for polishing copper containing surfaces
11/01/2001WO2001081203A1 Pod for carrying reticle cassette
11/01/2001WO2001081043A1 Process to minimize and/or eliminate conductive material coating over the top surface of a patterned substrate and layer structure made thereby
11/01/2001WO2001081042A1 Polishing method using a rehydrated dry particulate polishing composition
11/01/2001WO2001042766A3 Method and production of a sensor
11/01/2001WO2001027871A3 Method for production of contactless chip cards and for production of electrical units comprising chips with contact elements
11/01/2001WO2000057980A9 Efg crystal growth apparatus
11/01/2001WO2000039858A8 Metal gate double diffusion mosfet with improved switching speed and reduced gate tunnel leakage
11/01/2001US20010037487 Method of extracting characters and computer-readable recording medium
11/01/2001US20010037477 Enhanced embedded logic analyzer
11/01/2001US20010037160 Crosstalk cancellation circuit, interconnection module, interconnection method of automatic interconnection apparatus, and integrated circuit
11/01/2001US20010036998 Comprising di-, tri- and/or tetra-(alkoxy/phenoxy)silanes and a thermosetting resin which can be condensed therewith which has an absorption capacity with respect to exposing light; can be etched at high rate for fine resist patterns
11/01/2001US20010036805 Forming a transparent window in a polishing pad for a chemical mehcanical polishing apparatus
11/01/2001US20010036804 CMP polishing pad including a solid catalyst
11/01/2001US20010036799 Method of polishing silicon wafer
11/01/2001US20010036798 Methods for chemical-mechanical polishing of semiconductor wafers
11/01/2001US20010036797 Process for producing a semiconductor wafer
11/01/2001US20010036793 Method and apparatus for detecting an end-point in chemical mechanical polishing of metal layers
11/01/2001US20010036792 Method and apparatus for polishing semiconductor wafers
11/01/2001US20010036771 Method and apparatus for forming modular sockets using flexible interconnects and resulting structures
11/01/2001US20010036755 Method of fabricating semiconductor device
11/01/2001US20010036754 Flattened multilayer dielectric film
11/01/2001US20010036753 Method of forming an on-chip decoupling capacitor with bottom hardmask
11/01/2001US20010036752 Methods and apparatus for forming a high dielectric film and the dielectric film formed thereby
11/01/2001US20010036751 Method for forming a thin oxide layer using wet oxidation
11/01/2001US20010036750 Dual damascene anti-fuse with via before wire
11/01/2001US20010036749 Apparatus and methods for integrated circuit planarization
11/01/2001US20010036748 Compatibilization treatment
11/01/2001US20010036747 Method for the formation and lift-off of porous silicon layers
11/01/2001US20010036746 Methods of producing and polishing semiconductor device and polishing apparatus
11/01/2001US20010036745 Method of forming a mask
11/01/2001US20010036743 Mask for producing rectangular openings in a substrate
11/01/2001US20010036742 Two-piece chuck
11/01/2001US20010036741 Local etching apparatus and local etching method
11/01/2001US20010036740 CF4+H20 Plasma ashing for reduction of contact/via resistance
11/01/2001US20010036739 Interim oxidation of silsesquioxane dielectric for dual damascene process
11/01/2001US20010036738 Semiconductor device manufacturing method
11/01/2001US20010036737 Semiconductor device formed with metal wiring on a wafer by chemical mechanical polishing, and method of manufacturing the same
11/01/2001US20010036736 Method for manufacturing semiconductor device, and processing system and semiconductor device
11/01/2001US20010036735 Semiconductor device adapted for polishing
11/01/2001US20010036734 Method of formation of conductive lines on integrated circuits
11/01/2001US20010036733 Method of fabricating thin-film transistor
11/01/2001US20010036732 Method of manufacturing semiconductor device having minute gate electrodes
11/01/2001US20010036731 Process for making planarized silicon fin device
11/01/2001US20010036730 Method for fabricating a dram cell capacitor
11/01/2001US20010036728 Method of manufacturing semiconductor device
11/01/2001US20010036727 Semiconductor processing methods and integrated circuitry
11/01/2001US20010036726 Semiconductor device and method of manufacturing the same
11/01/2001US20010036725 Method for fabricating a bottom anti-reflectivity coating layer
11/01/2001US20010036723 Method of forming insulated metal interconnections in integrated circuits
11/01/2001US20010036722 Apparatus and manufacturing method for semiconductor device adopting an interlayer contact structure
11/01/2001US20010036721 Process for metallizing at least one insulating layer of a component
11/01/2001US20010036719 Integrated circuits
11/01/2001US20010036718 Stereolithographically fabricated conductive elements, semiconductor device components and assemblies including such conductive elements, and methods
11/01/2001US20010036717 Hot metallization process
11/01/2001US20010036716 Wire bonding to copper
11/01/2001US20010036714 Forming a oxide- nitride-oxide (ono) layer on the surface of the substrate, having a bottom oxide layer, a silicon nitride layer and a top tantalum pentoxide layer, deposited by chemical vapor deposition
11/01/2001US20010036713 Sidewall process and method of implantation for improved CMOS with benefit of low CGD, improved doping profiles, and insensitivity to chemical processing
11/01/2001US20010036712 A method of producing a semiconductor device having a source drain region of small junction depth
11/01/2001US20010036711 Semiconductor device and manufacturing method of the same
11/01/2001US20010036710 SOI structure semiconductor device and a fabrication method thereof
11/01/2001US20010036709 Low cost shallow trench isolation using non-conformal dielectric material
11/01/2001US20010036708 Method for forming a capacitor for semiconductor devices
11/01/2001US20010036706 Thermal processing apparatus for introducing gas between a target object and a cooling unit for cooling the target object
11/01/2001US20010036705 Semiconductor device and method of manufacturing the device
11/01/2001US20010036704 Trench semiconductor device manufacture with a thicker upper insulating layer
11/01/2001US20010036703 Method of manufacturing capacitor of semiconductor device
11/01/2001US20010036702 Integrated circuit having a micromagnetic device and method of manufacture therefor
11/01/2001US20010036701 Semiconductor processing methods of forming integrated circuitry memory devices, methods of forming capacitor containers, methods of making electrical connection to circuit nodes and related integrated circuitry
11/01/2001US20010036700 Method of fabricating cup-shape cylindrical capacitor of high density DRAMS
11/01/2001US20010036699 Multi-layer tunneling device with a graded stoichiometry insulating layer