H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof

Patents for H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof (658,974)
11/2001
11/13/2001	US6317866 Method of preparing charged particle beam drawing data and recording medium on which program thereof is recorded
11/13/2001	US6317865 Wiring-capacitance improvement aid device aiding in improvement of points having wiring-capacitance attributable error only with layout modification, method thereof, and medium having a program therefor recorded therein
11/13/2001	US6317864 System and method for graphic layout modification
11/13/2001	US6317860 Electronic design automation tool for display of design profile
11/13/2001	US6317647 Aligner
11/13/2001	US6317642 Apparatus and methods for uniform scan dispensing of spin-on materials
11/13/2001	US6317514 Method and apparatus for inspection of patterned semiconductor wafers
11/13/2001	US6317480 Method of manufacturing X-ray mask and X-ray mask blank, and X-ray mask and X-ray mask blank manufactured thereby
11/13/2001	US6317406 Device for gripping and holding a flat substrate
11/13/2001	US6317375 Method and apparatus for reading memory cells of a resistive cross point array
11/13/2001	US6317366 Dynamic random access memory
11/13/2001	US6317360 Flash memory and methods of writing and erasing the same as well as a method of forming the same
11/13/2001	US6317357 Vertical bipolar read access for low voltage memory cell
11/13/2001	US6317355 Nonvolatile ferroelectric memory device with column redundancy circuit and method for relieving failed address thereof
11/13/2001	US6317353 Semiconductor integrated circuit
11/13/2001	US6317344 Electrical device with booster circuit
11/13/2001	US6317333 Package construction of semiconductor device
11/13/2001	US6317305 Electrostatic discharge protection in semiconductor devices with reduced parasitic capacitance
11/13/2001	US6317274 Optical element
11/13/2001	US6317216 Optical method for the determination of grain orientation in films
11/13/2001	US6317211 Optical metrology tool and method of using same
11/13/2001	US6317198 Method of examining an exposure tool
11/13/2001	US6317195 Projection exposure apparatus
11/13/2001	US6317175 Single crystal silicon arrayed devices with optical shield between transistor and substrate
11/13/2001	US6317174 TFT array substrate, liquid crystal display using TFT array substrate, and manufacturing method thereof
11/13/2001	US6316985 Substrate voltage generating circuit provided with a transistor having a thin gate oxide film and a semiconductor integrated circuit device provided with the same
11/13/2001	US6316981 Signal distribution network on backside of substrate
11/13/2001	US6316975 Radio frequency data communications device
11/13/2001	US6316950 Method and apparatus for imaging semiconductor devices
11/13/2001	US6316901 Exposure apparatus and method utilizing isolated reaction frame
11/13/2001	US6316839 Mask repattern process
11/13/2001	US6316838 Semiconductor device
11/13/2001	US6316837 Area array type semiconductor package and fabrication method
11/13/2001	US6316836 Semiconductor device interconnection structure
11/13/2001	US6316835 Method for forming zig-zag bordered openings in semiconductor structures and structures formed
11/13/2001	US6316834 Tungsten plugs for integrated circuits and method for making same
11/13/2001	US6316833 Semiconductor device with multilayer interconnection having HSQ film with implanted fluorine and fluorine preventing liner
11/13/2001	US6316831 Microelectronic fabrication having formed therein terminal electrode structure providing enhanced barrier properties
11/13/2001	US6316830 Bumpless flip chip assembly with strips and via-fill
11/13/2001	US6316827 Semiconductor device having improved temperature distribution
11/13/2001	US6316825 Chip stack package utilizing a connecting hole to improve electrical connection between leadframes
11/13/2001	US6316824 Plastic leads frames for semiconductor devices
11/13/2001	US6316821 High density lead frames and methods for plastic injection molding
11/13/2001	US6316818 Vertical bipolar transistor including an extrinsic base with reduced roughness, and fabrication process
11/13/2001	US6316817 MeV implantation to form vertically modulated N+ buried layer in an NPN bipolar transistor
11/13/2001	US6316816 Film resistor and method of producing same
11/13/2001	US6316815 Structure for isolating integrated circuits in semiconductor substrate and method for making it
11/13/2001	US6316814 Solid imaging device
11/13/2001	US6316810 Display switch with double layered gate insulation and resinous interlayer dielectric
11/13/2001	US6316809 Analog MOSFET devices
11/13/2001	US6316806 Trench transistor with a self-aligned source
11/13/2001	US6316804 Oxygen implant self-aligned, floating gate and isolation structure
11/13/2001	US6316803 Integrated circuit memory devices having self-aligned contact
11/13/2001	US6316802 Easy to manufacture integrated semiconductor memory configuration with platinum electrodes
11/13/2001	US6316801 Semiconductor device having capacitive element structure and multilevel interconnection structure and method of fabricating the same
11/13/2001	US6316800 Boride electrodes and barriers for cell dielectrics
11/13/2001	US6316799 Memory cell, method of controlling same and method of manufacturing same
11/13/2001	US6316798 Ferroelectric memory device and method for manufacturing the same
11/13/2001	US6316797 Scalable lead zirconium titanate(PZT) thin film material and deposition method, and ferroelectric memory device structures comprising such thin film material
11/13/2001	US6316795 Silicon-carbon emitter for silicon-germanium heterojunction bipolar transistors
11/13/2001	US6316794 Lateral high voltage semiconductor device with protective silicon nitride film in voltage withstanding region
11/13/2001	US6316793 Nitride based transistors on semi-insulating silicon carbide substrates
11/13/2001	US6316789 Semiconductor device and method for producing the same
11/13/2001	US6316787 Semiconductor integrated circuit and fabrication method thereof
11/13/2001	US6316785 Nitride-compound semiconductor device
11/13/2001	US6316754 Frequency selected, variable output inductor heater system
11/13/2001	US6316748 Apparatus for manufacturing a semiconductor device
11/13/2001	US6316747 Apparatus for the thermal treatment of substrates
11/13/2001	US6316565 For forming patterns of integrated semiconductor device, resolution in photolithography
11/13/2001	US6316372 Methods of forming a layer of silicon nitride in a semiconductor fabrication process
11/13/2001	US6316371 Method for the chemical treatment of a semiconductor substrate
11/13/2001	US6316370 Method for etching doped polysilicon with high selectivity to undoped polysilicon
11/13/2001	US6316369 Corrosion-resistant system and method for a plasma etching apparatus
11/13/2001	US6316368 Method of fabricating a node contact
11/13/2001	US6316367 Process and device for handling disk-like objects, especially silicon wafers
11/13/2001	US6316365 Chemical-mechanical polishing method
11/13/2001	US6316364 Polishing method and polishing solution
11/13/2001	US6316363 Deadhesion method and mechanism for wafer processing
11/13/2001	US6316362 Method for manufacturing semiconductor device
11/13/2001	US6316361 CVD reactor and process for producing an epitally coated semiconductor wafer
11/13/2001	US6316360 High aspect ratio metallization structures for shallow junction devices, and methods of forming the same
11/13/2001	US6316359 Interconnect structure in a semiconductor device and method of formation
11/13/2001	US6316358 Method for fabricating an integrated circuit device
11/13/2001	US6316357 Method for forming metal silicide by laser irradiation
11/13/2001	US6316356 Thermal processing of metal alloys for an improved CMP process in integrated circuit fabrication
11/13/2001	US6316355 Method for forming metal wire using titanium film in semiconductor device having contact holes
11/13/2001	US6316354 Process for removing resist mask of integrated circuit structure which mitigates damage to underlying low dielectric constant silicon oxide dielectric layer
11/13/2001	US6316353 Method of forming conductive connections
11/13/2001	US6316352 Method of fabricating a bottom electrode
11/13/2001	US6316351 Inter-metal dielectric film composition for dual damascene process
11/13/2001	US6316350 Post fuse slag etch
11/13/2001	US6316349 Method for forming contacts of semiconductor devices
11/13/2001	US6316348 High selectivity Si-rich SiON etch-stop layer
11/13/2001	US6316347 Air gap semiconductor structure and method of manufacture
11/13/2001	US6316345 High-temperature fluorinated chemistry removal of contact BARC layer
11/13/2001	US6316344 Method for forming gate
11/13/2001	US6316341 Method for cell pass transistor design in DRAM process
11/13/2001	US6316340 Photolithographic process for preventing corner rounding
11/13/2001	US6316339 Semiconductor device and production method thereof
11/13/2001	US6316338 Laser annealing method

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