Patents
Sitemap › H01 - Basic electric elements › H01L - Semiconductor devices; Electric solid state devices not otherwise provided for › H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
Patents for H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof (658,974)
11/2001
11/20/2001US6320229 Semiconductor device
11/20/2001US6320227 Semiconductor memory device and method for fabricating the same
11/20/2001US6320226 LCD with increased pixel opening sizes
11/20/2001US6320225 SOI CMOS body contact through gate, self-aligned to source- drain diffusions
11/20/2001US6320224 Method for producing a semiconductor integrated circuit including a thin film transistor and a capacitor
11/20/2001US6320222 Structure and method for reducing threshold voltage variations due to dopant fluctuations
11/20/2001US6320221 TFT-LCD having a vertical thin film transistor
11/20/2001US6320219 Memory cell for EEPROM devices and corresponding fabricating process
11/20/2001US6320218 Non-volatile semiconductor memory device and manufacturing method thereof
11/20/2001US6320217 Semiconductor memory device
11/20/2001US6320216 Memory device with barrier portions having defined capacitance
11/20/2001US6320215 Crystal-axis-aligned vertical side wall device
11/20/2001US6320214 Semiconductor device having a ferroelectric TFT and a dummy element
11/20/2001US6320213 Diffusion barriers between noble metal electrodes and metallization layers, and integrated circuit and semiconductor devices comprising same
11/20/2001US6320212 Superlattice fabrication for InAs/GaSb/AISb semiconductor structures
11/20/2001US6320211 Semiconductor device and electronic device by use of the semiconductor
11/20/2001US6320210 Hetero-junction field effect transistor
11/20/2001US6320209 Accuracy
11/20/2001US6320208 II-VI compound semiconductor device
11/20/2001US6320207 Light emitting device having flat growth GaN layer
11/20/2001US6320205 Edge termination for a semiconductor component, a schottky diode having an edge termination, and a method for producing the schottky diode
11/20/2001US6320204 Electro-optical device in which an extending portion of a channel region of a semiconductor layer is connected to a capacitor line and an electronic apparatus including the electro-optical device
11/20/2001US6320203 Method for fabricating a simplified CMOS polysilicon thin film transistor and resulting structure
11/20/2001US6320202 Bottom-gated thin film transistors comprising germanium in a channel region
11/20/2001US6320198 Charged particle beam lithography apparatus for forming pattern on semi-conductor
11/20/2001US6320187 Magnification and rotation calibration patterns for particle beam projection system
11/20/2001US6320158 Method and apparatus of fabricating perforated plate
11/20/2001US6320154 Plasma processing method
11/20/2001US6320138 Wiring substrate; for use in reduction in resistance and the occurrence of deformations in thin film
11/20/2001US6320127 Method and structure for reducing the incidence of voiding in an underfill layer of an electronic component package
11/20/2001US6319885 Cleaning solutions including nucleophilic amine compound having reduction and oxidation potentials
11/20/2001US6319861 Method of improving deposition
11/20/2001US6319860 Process for manufacturing semiconductor integrated circuit device including treatment of gas used in the process
11/20/2001US6319859 Borderless vias with HSQ gap filled metal patterns having high etching resistance
11/20/2001US6319858 Methods for reducing a dielectric constant of a dielectric film and for forming a low dielectric constant porous film
11/20/2001US6319857 Method of fabricating stacked N-O-N ultrathin gate dielectric structures
11/20/2001US6319856 Methods of forming dielectric layers and methods of forming capacitors
11/20/2001US6319855 Uniform dielectric film; integrated circuits
11/20/2001US6319854 Forming coating film by applying organic acid solution having silanol condensate particles on semiconductor substrate, heat treating coating film and vaporizing organic acid
11/20/2001US6319853 Method of manufacturing a semiconductor device using a minute resist pattern, and a semiconductor device manufactured thereby
11/20/2001US6319852 Nanoporous dielectric thin film formation using a post-deposition catalyst
11/20/2001US6319851 Method for packaging semiconductor device having bump electrodes
11/20/2001US6319850 Forming dielectric layer on semiconductor substrate; doping with ionized carbon tetrafluoride, chlorotrifluoromethane, dichlorodifluoromethane, trichlorofluoromethane, annealing while feeding gas
11/20/2001US6319849 Semiconductor device and a process for forming a protective insulating layer thereof
11/20/2001US6319848 Inhomogenous composite doped film for low temperature reflow
11/20/2001US6319847 Semiconductor device using a thermal treatment of the device in a pressurized steam ambient as a planarization technique
11/20/2001US6319846 Method for removing solder bodies from a semiconductor wafer
11/20/2001US6319845 Method of purifying alkaline solution and method of etching semiconductor wafers
11/20/2001US6319844 Method of manufacturing semiconductor device with via holes reaching interconnect layers having different top-surface widths
11/20/2001US6319843 Contacting nitride containing film with oxidizing plasma containing oxygen prior to deposition of acid catalyzed photoresist over film for minimizing or preventing contamination of photoresist
11/20/2001US6319842 Method of cleansing vias in semiconductor wafer having metal conductive layer
11/20/2001US6319841 Semiconductor processing using vapor mixtures
11/20/2001US6319840 For mol integration
11/20/2001US6319838 Lever arm for a scanning microscope
11/20/2001US6319837 Technique for reducing dishing in Cu-based interconnects
11/20/2001US6319836 Planarization system
11/20/2001US6319835 Stripping method
11/20/2001US6319834 Method and apparatus for improved planarity metallization by electroplating and CMP
11/20/2001US6319833 Forming a copper (cu) or cu alloy interconnection pattern comprising a dense array of spaced apart cu or cu alloy lines bordering open dielectric field on surface of wafer; spraying the wafer with a chemical agent to remove dielectric material
11/20/2001US6319832 Methods of making semiconductor devices
11/20/2001US6319831 Gap filling by two-step plating
11/20/2001US6319830 Process of fabricating semiconductor device
11/20/2001US6319828 Method for manufacturing a chip scale package having copper traces selectively plated with gold
11/20/2001US6319826 Method of fabricating barrier layer
11/20/2001US6319825 Metallization process of semiconductor device
11/20/2001US6319824 Method of forming a contact hole in a semiconductor device
11/20/2001US6319823 Process for forming a borderless via in a semiconductor device
11/20/2001US6319822 Process for forming an integrated contact or via
11/20/2001US6319821 Dual damascene approach for small geometry dimension
11/20/2001US6319820 Fabrication method for dual damascene structure
11/20/2001US6319819 Process for passivating top interface of damascene-type Cu interconnect lines
11/20/2001US6319818 Pattern factor checkerboard for planarization
11/20/2001US6319817 Method of forming viahole
11/20/2001US6319815 Electric wiring forming method with use of embedding material
11/20/2001US6319814 Method of fabricating dual damascene
11/20/2001US6319813 Semiconductor processing methods of forming integrated circuitry and integrated circuitry constructions
11/20/2001US6319812 Method of manufacturing a semiconductor device
11/20/2001US6319810 Method for forming solder bumps
11/20/2001US6319809 Method to reduce via poison in low-k Cu dual damascene by UV-treatment
11/20/2001US6319808 Ohmic contact to semiconductor devices and method of manufacturing the same
11/20/2001US6319807 Method for forming a semiconductor device by using reverse-offset spacer process
11/20/2001US6319806 Integrated circuit wiring and fabricating method thereof
11/20/2001US6319805 Semiconductor device having metal silicide film and manufacturing method thereof
11/20/2001US6319804 Process to separate the doping of polygate and source drain regions in dual gate field effect transistors
11/20/2001US6319803 Method of fabricating semiconductor device
11/20/2001US6319802 T-gate formation using modified damascene processing with two masks
11/20/2001US6319801 Method for cleaning a substrate and cleaning solution
11/20/2001US6319800 Static memory cell
11/20/2001US6319798 Method for reducing lateral dopant gradient in source/drain extension of MOSFET
11/20/2001US6319797 Process for manufacturing a semiconductor device
11/20/2001US6319796 Manufacture of an integrated circuit isolation structure
11/20/2001US6319795 Method for fabricating VLSI devices having trench isolation regions
11/20/2001US6319794 Structure and method for producing low leakage isolation devices
11/20/2001US6319792 Providing first and second chip regions on silicon wafer, wherein first resist pattern for semiconductor device is to be formed in first chip region, and second chip region includes a plurality of evaluation regions, determining data rate
11/20/2001US6319791 Semiconductor device manufacturing method and semiconductor device
11/20/2001US6319790 Process for fabricating semiconductor device with multiple cylindrical capacitor
11/20/2001US6319789 Method for improved processing and etchback of a container capacitor
11/20/2001US6319788 Semiconductor structure and manufacturing methods
11/20/2001US6319787 Method for forming a high surface area trench capacitor
11/20/2001US6319786 Self-aligned bipolar transistor manufacturing method
1 ... 5213 5214 5215 5216 5217 5218 5219 5220 5221 5222 5223 5224 5225 5226 5227 5228 5229 5230 5231 5232 5233 ... 6590