Patents
Patents for H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof (658,974)
11/2001
11/22/2001WO2001088973A1 Gate etch process for 12 inch wafers
11/22/2001WO2001088972A1 Process for producing integrated circuits
11/22/2001WO2001088970A1 Semiconductor wafer thinning method, and thin semiconductor wafer
11/22/2001WO2001088969A2 Improved capacitor electrodes
11/22/2001WO2001088968A1 Method for processing thin film and apparatus for processing thin film
11/22/2001WO2001088966A2 Method of adjusting the thickness of an electrode in a plasma processing system
11/22/2001WO2001088964A1 Arrangement for shipping and tansporting disc-like objects
11/22/2001WO2001088963A1 Device and method for treating, storing and loading supports for disk-shaped articles
11/22/2001WO2001088962A1 Plasma etching equipment
11/22/2001WO2001088960A2 Method of molecular-scale pattern imprinting at surfaces
11/22/2001WO2001088955A2 Method of monitoring ion implants by examination of an overlying masking material
11/22/2001WO2001088954A2 Method of and apparatus for making electrical contact to wafer surface for full-face electroplating or electropolishing
11/22/2001WO2001088950A1 Plasma etching system
11/22/2001WO2001088767A1 Integrated circuit partitioning, placement and routing system
11/22/2001WO2001088612A1 Photolithographically-patterned out-of-plane coil structures and method of making
11/22/2001WO2001088551A1 Probe card and method of producing the same
11/22/2001WO2001088514A1 Apparatus for inspection of semiconductor wafers and masks using a low energy electron micoscope with two illuminating beams
11/22/2001WO2001088229A1 Method and apparatus for end-point detection
11/22/2001WO2001087541A2 Pneumatic diaphragm head having an independent retaining ring and multi-region pressure control, and method to use the same
11/22/2001WO2001087534A2 Method and system for precisely positioning a waist of a material-processing laser beam to process microstructures within a laser-processing site
11/22/2001WO2001087529A1 Method for producing a structural member from plates stacked on top of each other and soldered together
11/22/2001WO2001087505A1 Supercritical fluid cleaning process for precision surfaces
11/22/2001WO2001050511B1 Semiconductor manufacture using helium-assisted etch
11/22/2001WO2001041544A3 Deposition of gate stacks including silicon germanium layers
11/22/2001WO2001035466A3 Field effect transistor with a body zone
11/22/2001WO2001033625A8 Electrostatic wafer clamp having electrostatic seal for retaining gas
11/22/2001WO2001032297A3 Modular chemical treatment system
11/22/2001WO2001027972A3 Molecular scale electronic devices
11/22/2001WO2000038238A9 Reduced diffusion of a mobile ion from a metal oxide ceramic into the substrate
11/22/2001WO2000013226A9 Process for preparing an ideal oxygen precipitating silicon wafer
11/22/2001US20010044926 Wiring connection checking apparatus and method for CAD system and recording medium on which program therefor is recorded
11/22/2001US20010044925 Circuit design method for designing conductive members with a multilayered structure to have antenna sized of proper values
11/22/2001US20010044924 Logic circuit module, method for designing a semiconductor integrated circuit using the same, and semiconductor integrated circuit
11/22/2001US20010044923 Memory embedded semiconductor integrated circuit and a method for designing the same
11/22/2001US20010044918 Semiconductor integrated circuit and design method and manufacturing method of the same
11/22/2001US20010044669 System and method to reduce bond program errors of integrated circuit bonders
11/22/2001US20010044667 System of manufacturing semiconductor intergrated circuit
11/22/2001US20010044270 Polishing apparatus
11/22/2001US20010044268 Carrier head for a chemical mechanical polishing apparatus
11/22/2001US20010044266 Polishing apparatus
11/22/2001US20010044264 Polishing composition
11/22/2001US20010044263 Polish pad with non-uniform groove depth to improve wafer polish rate uniformity
11/22/2001US20010044262 Apparatus and methods for substantial planarization of solder bumps
11/22/2001US20010044260 CMP polishing slurry dewatering and reconstitution
11/22/2001US20010044256 Cutting machine
11/22/2001US20010044225 Method for forming microelectronic spring structures on a substrate
11/22/2001US20010044222 Method for forming a nitridized interface on a semiconductor substrate
11/22/2001US20010044221 Semiconductor processing methods of forming and utilizing antireflective material layers, and methods of forming transistor gate stacks
11/22/2001US20010044220 Method Of Forming Silicon Oxynitride Films
11/22/2001US20010044219 Method and apparatus for stabilizing high pressure oxidation of a semiconductor device
11/22/2001US20010044218 Semiconductor processing methods of forming photoresist over silicon nitride materials
11/22/2001US20010044216 Porous region removing method and semiconductor substrate manufacturing method
11/22/2001US20010044215 Causing silicon layer to contact with a gas selected from a group of the air, oxygen and ozone under heated conditions, for causing silylyzation to occur for contaminants to cleave a benzene ring of the contaminant
11/22/2001US20010044214 Method for dry-etching a titanium nitride containing multilayer film
11/22/2001US20010044213 Method of anisotropic etching of substrates
11/22/2001US20010044212 Techniques for improving etching in a plasma processing chamber
11/22/2001US20010044211 Removal of copper oxides from integrated interconnects
11/22/2001US20010044210 Fabrication method for semiconductor integrated circuit device
11/22/2001US20010044209 Method for modification of polishing pattern dependence in chemical mechanical polishing
11/22/2001US20010044208 Etchant and method for fabricating a semiconductor device using the same
11/22/2001US20010044207 Providing the stream of platinum containing precursor including an organic group and a stream of oxygen containing gas in the region of the surface of the substrate to deposit low carbon or carbon-free platinum on the surface
11/22/2001US20010044205 Forming a second conductive material in said recess so as to have a top surface which is substatnially planer and coestensive with top surface of dielectric layer
11/22/2001US20010044204 Method for making semiconductor devices having gradual slope contacts
11/22/2001US20010044203 Surface treatment of low-k siof to prevent metal interaction
11/22/2001US20010044202 Method of preventing copper poisoning in the fabrication of metal interconnects
11/22/2001US20010044201 Semiconductor device having a multilayer interconnection structure
11/22/2001US20010044200 Nanoscale patterning for the formation of extensive wires
11/22/2001US20010044199 Semiconductor device and manufacture thereof
11/22/2001US20010044198 Repairable flip chip semiconductor device with excellent packaging reliability and method of manufacturing same
11/22/2001US20010044197 Wafer-scale assemby of chip-size packages
11/22/2001US20010044196 Semiconductor device and method for producing the same
11/22/2001US20010044195 Buried layer manufacturing method
11/22/2001US20010044194 Bonded substrate structures and method for fabricating bonded substrate structures
11/22/2001US20010044193 Isolation structure and process therefor
11/22/2001US20010044192 Method for manufacturing stacked capacitor with stable capacitor lower electrode
11/22/2001US20010044191 Method for manufacturing semiconductor device
11/22/2001US20010044190 Method of fabricating memory cell with trench capacitor and vertical transistor
11/22/2001US20010044189 Method of fabricating memory cell with vertical transistor
11/22/2001US20010044188 Method of fabricating memory cell
11/22/2001US20010044187 Method for forming gate electrode of flash memory
11/22/2001US20010044186 Method for reducing single bit data loss in a memory circuit
11/22/2001US20010044185 Memory device, manufacturing method thereof and integrated circuit thereof
11/22/2001US20010044184 Nonvolatile semiconductor memory device and method of manufacturing the same
11/22/2001US20010044183 Nonvolatile semiconductor device having a memory cells each of which is constituted of a memory transistor and a selection transistor
11/22/2001US20010044182 Semiconductor device having hsg polycrystalline silicon layer
11/22/2001US20010044181 Semiconductor device and method for fabricating the same
11/22/2001US20010044180 Trench capacitor and method for fabricating a trench capacitor
11/22/2001US20010044179 Method for manufacturing a capacitor
11/22/2001US20010044178 Method of forming dielectric film with good crystallinity and low leak
11/22/2001US20010044176 Manufacturing process of a high integration density power mos device
11/22/2001US20010044175 Micro heating of selective regions
11/22/2001US20010044174 Semiconductor device and method of fabricating the same
11/22/2001US20010044173 Annealing the fluorine containing layer to drive fluorine from the fluorine containing layer into polycrystalline thin film, incorporating fluorine within the grain boundaries to passivate the grain bounderies without chemical reaction
11/22/2001US20010044172 Method for fabricating thin film transistor
11/22/2001US20010044171 Ball grid array (BGA) encapsulation mold
11/22/2001US20010044170 Method for resin coating of semiconductor device, coating resin and liquid crystal display device
11/22/2001US20010044169 Lead frame for semiconductor devices, a semiconductor device made using the lead frame, and a method of manufacturing a semiconductor device
11/22/2001US20010044164 Capacitor containing amorphous and polycrystalline ferroelectric films and fabrication method therefor, and method for forming amorphous ferroelectric film
11/22/2001US20010044163 Sheet manufacturing method, sheet, sheet manufacturing apparatus, and solar cell
11/22/2001US20010044162 Method and apparatus for fabricating electronic device