H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof

Patents for H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof (658,974)
11/2001
11/29/2001	WO2001090686A1 In-situ mirror characterization
11/29/2001	WO2001090446A2 Method and apparatus to overcome anomalies in copper seed layers and to tune for feature size and aspect ratio
11/29/2001	WO2001090439A1 Method for making an extreme ultraviolet microlithography transmission modulator and resulting modulator
11/29/2001	WO2001090434A2 Tuning electrodes used in a reactor for electrochemically processing a microelectronic workpiece
11/29/2001	WO2001090015A1 Solution for treating surface of glass and treatment method
11/29/2001	WO2001090014A1 Etching process
11/29/2001	WO2001089767A2 A chemical-mechanical polishing system for the manufacture of semiconductor devices
11/29/2001	WO2001089765A1 In-situ endpoint detection and process monitoring method and apparatus for chemical mechanical polishing
11/29/2001	WO2001089763A2 Multilayer retaining ring for chemical mechanical polishing
11/29/2001	WO2001089753A1 Improved apparatus and method for dispensing solder
11/29/2001	WO2001089745A1 Porous heat sink for forced convective flow and method of making therefore
11/29/2001	WO2001089728A1 Apparatus and process for cleaning a work piece
11/29/2001	WO2001089713A1 Adhesive dispensing and vision system for an automatic assembly system
11/29/2001	WO2001089284A2 Trench capacitor with insulation collar stack, and method of forming thereof
11/29/2001	WO2001075967B1 In situ and ex situ etching process for sti with oxide collar application
11/29/2001	WO2001054853A3 Method and apparatus for repair of defects in materials with short laser pulses
11/29/2001	WO2001046680A3 Reticle for use in photolithography and methods for making same and inspecting
11/29/2001	WO2001024259A3 Semiconductor packaging
11/29/2001	WO2000054941A9 Wafer gripping fingers
11/29/2001	WO2000020519A3 Preparations containing fine-particulate inorganic oxides
11/29/2001	US20010047496 Semiconductor test device for conducting an operation test in parallel on many chips in a wafer test and semiconductor test method
11/29/2001	US20010047366 System and method to recreate illumination conditions on integrated circuit bonders
11/29/2001	US20010047225 Substrate conveying system in semiconductor manufacturing apparatus
11/29/2001	US20010047222 Reticle management system
11/29/2001	US20010047216 Service method, service system and manufacturing/inspection apparatus
11/29/2001	US20010046933 Sol-gel-based composite materials for direct-write electronics applications
11/29/2001	US20010046832 Apparatus and methods for substantial planarization of solder bumps
11/29/2001	US20010046831 Improved methods and apparatus for chemical mechanical planarization (cmp) of a semiconductor wafer
11/29/2001	US20010046792 Method of forming oxynitride film or the like and system for carrying out the same
11/29/2001	US20010046791 Use of silicon oxynitride arc for metal layers
11/29/2001	US20010046790 Etching mask and magnetic head device
11/29/2001	US20010046789 Semiconductor device and method for manufacturing the same
11/29/2001	US20010046788 Method for fabricating thin insulating films, a semiconductor device and a method for fabricating a semiconductor device
11/29/2001	US20010046787 Method for forming a dielectric on a semiconductor substrate
11/29/2001	US20010046786 High-temperature high-pressure processing method for semiconductor wafers, and an anti-oxidizing body used for the method
11/29/2001	US20010046785 Enhancement, stabilization and metallization of porous silicon
11/29/2001	US20010046784 Method of manufacturing a semiconductor device
11/29/2001	US20010046783 Semiconductor device and manufacturing method thereof
11/29/2001	US20010046782 Method for forming contact window
11/29/2001	US20010046781 Method for etching organic film, method for fabricating semiconductor device and pattern formation method
11/29/2001	US20010046780 Using plasma generated from a gas including an amine such as methylamine.
11/29/2001	US20010046779 Plasma etching methods
11/29/2001	US20010046778 Dual damascene process using sacrificial spin-on materials
11/29/2001	US20010046777 Method for forming a dielectric layer
11/29/2001	US20010046776 Method for fabricating a stencil mask
11/29/2001	US20010046775 Method for forming semiconductor device to prevent electric field concentration from being generated at corner of active region
11/29/2001	US20010046774 Planarization system with multiple polishing pads
11/29/2001	US20010046773 Composition for polishing metal on semiconductor wafer and method of using same
11/29/2001	US20010046772 Semiconductor processing methods of forming a conductive projection and methods of increasing alignment tolerances
11/29/2001	US20010046771 Thin film resistor having improved temperature independence and a method of engineering the TCR of the thin film resistor
11/29/2001	US20010046769 Waferless seasoning process
11/29/2001	US20010046768 Methods and apparatus for thermally processing wafers
11/29/2001	US20010046767 Method and apparatus for manufacturing semiconductor device
11/29/2001	US20010046766 Semiconductor devices and methods for manufacturing the same
11/29/2001	US20010046765 Method for producing a barrier layer in an electronic component and method for producing an electronic component with a barrier layer
11/29/2001	US20010046764 Semiconductor device and manufacturing method thereof
11/29/2001	US20010046763 Method for creating a die shrink insensitive semiconductor package and component therefor
11/29/2001	US20010046762 Method for manufacturing semiconductor device having trench filled with polysilicon
11/29/2001	US20010046761 Method of fabricating contact pads of a semiconductor device
11/29/2001	US20010046760 Transistor having improved gate structure
11/29/2001	US20010046759 Method of manufacturing a gate electrode with low resistance metal layer remote from a semiconductor
11/29/2001	US20010046758 Implantation method for simultaneously implanting in one region and blocking the implant in another region
11/29/2001	US20010046757 Method for fabricating semiconductor device
11/29/2001	US20010046756 Efficient fabrication process for dual well type structures
11/29/2001	US20010046755 By uniformly arranging vias around the bump on an integrated circuit, current can uniformly flow to and from the bump, effectively leading to reduced current density around the bump.
11/29/2001	US20010046754 Process for fabricating semiconductor device
11/29/2001	US20010046753 Method for forming a self-aligned isolation trench
11/29/2001	US20010046752 Method of improving alignment for semiconductor fabrication
11/29/2001	US20010046751 Method of making a self-aligned recessed container cell capacitor
11/29/2001	US20010046750 Method for manufacturing semiconductor device having a STI structure
11/29/2001	US20010046748 Methodology for high-performance, high reliability input/output devices and analog-compatible input/output and core devices using core device implants
11/29/2001	US20010046747 Heterojunction bipolar transistor and manufacturing method therefor
11/29/2001	US20010046746 Method of fabricating an SOI wafer and SOI wafer fabricated by the method
11/29/2001	US20010046745 Forming p-type halo surrounding n+ bitline diffusion region allows normally implanted channel doping concentration to be greatly reduced, thus achieving improved array threshold voltage control without increased node diffusion leakage
11/29/2001	US20010046744 Transistor with reduced series resistance junction regions
11/29/2001	US20010046743 Method for forming dual-polysilicon structures using a built- in stop layer
11/29/2001	US20010046742 Barrier in gate stack for improved gate dielectric integrity
11/29/2001	US20010046741 Integrated circuitry comprisihg multipe transistors with different channel lengths
11/29/2001	US20010046740 Low cost solution to integrate two different mosfet designs on a chip
11/29/2001	US20010046738 Method of forming high k tantalum pentoxide ta205 instead of ono stacked films to increase coupling ratio and improve reliability for flash memory devices
11/29/2001	US20010046737 Semiconductor memory device and fabricating method thereof
11/29/2001	US20010046736 Method for manufacturing a buried gate
11/29/2001	US20010046735 Integrated circuit structure comprising capacitor element and corresponding manufacturing process
11/29/2001	US20010046734 Methods of forming resistors
11/29/2001	US20010046733 Semiconductor device having electrical divided substrate and method for fabricating the semiconductor device
11/29/2001	US20010046732 Angled implant to improve high current operation of bipolar transistors
11/29/2001	US20010046731 Semiconductor device architectures including UV transmissive nitride layers
11/29/2001	US20010046730 Method of designing/manufacturing semiconductor integrated circuit device using combined exposure pattern and semiconductor integrated circuit device
11/29/2001	US20010046729 Method of manufacturing a semiconductor device
11/29/2001	US20010046728 Method of forming conductive lines
11/29/2001	US20010046727 Method for fabricating a gate conductive structure
11/29/2001	US20010046725 High density cavity-up wire bond BGA
11/29/2001	US20010046724 Molded ball grid array
11/29/2001	US20010046721 Method for reworking metal layers on integrated circuit bond pads
11/29/2001	US20010046720 Method of detecting and monitoring stresses in a semiconductor wafer
11/29/2001	US20010046719 Pattern-forming method using photomask, and pattern-forming apparatus
11/29/2001	US20010046717 Semiconductor device having ferroelectric thin film and fabricating method therefor
11/29/2001	US20010046716 Method for manufacturing a semiconductor device
11/29/2001	US20010046715 Semiconductor device test probe, manufacturing method therefor and semiconductor device tested by the probe
11/29/2001	US20010046695 Method of forming silicide

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