Patents
Sitemap › H01 - Basic electric elements › H01L - Semiconductor devices; Electric solid state devices not otherwise provided for › H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
Patents for H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof (658,974)
08/2002
08/20/2002US6436832 Method to reduce polish initiation time in a polish process
08/20/2002US6436831 Methods of forming insulative plugs and oxide plug forming methods
08/20/2002US6436830 Delivering processed slurry to the polishing device. the slurry processor including a metal separator for separating metal particles, polished from the semiconductor wafer, from the used slurry. the slurry can be continuously recirculated
08/20/2002US6436829 Two phase chemical/mechanical polishing process for tungsten layers
08/20/2002US6436828 Chemical mechanical polishing using magnetic force
08/20/2002US6436827 Fabrication method of a semiconductor device
08/20/2002US6436826 Chemical enhancer layer formed on damascene pattern which is filled with copper using mocvd; enhancer exposed to plasma or radical plasma process so that it remains only within a bottom portion of damascene pattern.
08/20/2002US6436825 Method of copper barrier layer formation
08/20/2002US6436824 Low dielectric constant materials for copper damascene
08/20/2002US6436823 Method for forming a TiN layer on top of a metal silicide layer in a semiconductor structure and structure formed
08/20/2002US6436822 Method for making a carbon doped oxide dielectric material
08/20/2002US6436820 Method for the CVD deposition of a low residual halogen content multi-layered titanium nitride film having a combined thickness greater than 1000 Å
08/20/2002US6436819 Formation of a metal nitride/metal stack suitable for use as a barrier/liner exposed to a treatment step in a nitrogen-containing environment, e.g., a plasma. the plasma treatment modifies the entire metal nitride layer
08/20/2002US6436818 Semiconductor structure having a doped conductive layer
08/20/2002US6436817 Method for manufacturing a copper interconnection with an aluminum oxide-conductive layer stack barrier layer in semiconductor memory device
08/20/2002US6436816 Patterns to form an interconnect; said metal layer composed of a material selected from the group consisting of ni, cu, and palladium,
08/20/2002US6436815 Electro-optical device and method for driving the same
08/20/2002US6436814 Interconnection structure and method for fabricating same
08/20/2002US6436813 Interlayer insulating film formed on one main surface of the semiconductor substrate and having a concave portion, a liner film formed on the inner surface of concave wire layer
08/20/2002US6436812 Multilayer; etch barrier, hard mask and antireflectivity layer
08/20/2002US6436811 Method of forming a copper-containing metal interconnect using a chemical mechanical planarization (CMP) slurry
08/20/2002US6436810 Bi-layer resist process for dual damascene
08/20/2002US6436809 Method of manufacturing semiconductor devices, etching compositions for manufacturing semiconductor devices, and semiconductor devices made using this method
08/20/2002US6436808 NH3/N2-plasma treatment to prevent organic ILD degradation
08/20/2002US6436807 Method for making an interconnect layer and a semiconductor device including the same
08/20/2002US6436806 Semiconductor device manufacturing method for preventing electrical shorts between lower and upper interconnection layers
08/20/2002US6436805 Local interconnect structures and methods for making the same
08/20/2002US6436804 Semiconductor integrated circuit device, semiconductor integrated circuit wiring method, and cell arranging method
08/20/2002US6436801 Hafnium nitride gate dielectric
08/20/2002US6436800 Method for fabricating a non-volatile memory with a shallow junction
08/20/2002US6436799 Process for annealing semiconductors and/or integrated circuits
08/20/2002US6436798 MOSFET device
08/20/2002US6436797 Apparatus and method for forming a deposited film on a substrate
08/20/2002US6436796 Systems and methods for epitaxial processing of a semiconductor substrate
08/20/2002US6436795 Process for producing semiconductor chip
08/20/2002US6436794 Process flow for ARS mover using selenidation wafer bonding before processing a media side of a rotor wafer
08/20/2002US6436793 Methods of forming semiconductor structure
08/20/2002US6436792 Method of manufacturing semiconductor device
08/20/2002US6436791 Method of manufacturing a very deep STI (shallow trench isolation)
08/20/2002US6436790 Method for fabrication semiconductor device having trench isolation structure
08/20/2002US6436789 Method of forming a device separation region
08/20/2002US6436787 Method of forming crown-type MIM capacitor integrated with the CU damascene process
08/20/2002US6436786 Method for fabricating a semiconductor device
08/20/2002US6436783 Method of forming MOS transistor
08/20/2002US6436782 Process for fabricating a self-aligned double-polysilicon bipolar transistor
08/20/2002US6436781 High speed and low parasitic capacitance semiconductor device and method for fabricating the same
08/20/2002US6436780 Semiconductor device
08/20/2002US6436778 Re-oxidation approach to improve peripheral gate oxide integrity in a tunnel nitride oxidation process
08/20/2002US6436777 Semiconductor device and manufacturing method thereof
08/20/2002US6436776 Process for fabricating a aligned LDD transistor
08/20/2002US6436775 MOSFET device fabrication method capable of allowing application of self-aligned contact process while maintaining metal gate to have uniform thickness
08/20/2002US6436774 Method for forming variable-K gate dielectric
08/20/2002US6436773 Fabrication of test field effect transistor structure
08/20/2002US6436772 Method of manufacturing semiconductor device having memory cell transistors
08/20/2002US6436771 Method of forming a semiconductor device with multiple thickness gate dielectric layers
08/20/2002US6436770 Method to control the channel length of a vertical transistor by first forming channel using selective epi and source/drain using implantation
08/20/2002US6436769 Split gate flash memory with virtual ground array structure and method of fabricating the same
08/20/2002US6436768 Source drain implant during ONO formation for improved isolation of SONOS devices
08/20/2002US6436767 Semiconductor memory device and process for manufacturing the same
08/20/2002US6436766 Process for fabricating high density memory cells using a polysilicon hard mask
08/20/2002US6436765 Method of fabricating a trenched flash memory cell
08/20/2002US6436764 Method for manufacturing a flash memory with split gate cells
08/20/2002US6436763 Process for making embedded DRAM circuits having capacitor under bit-line (CUB)
08/20/2002US6436762 Method for improving bit line to capacitor electrical failures on DRAM circuits using a wet etch-back to improve the bit-line-to-capacitor overlay margins
08/20/2002US6436761 Method for manufacturing semiconductor memory devices
08/20/2002US6436760 Method for reducing surface oxide in polysilicon processing
08/20/2002US6436759 Method for fabricating a MOS transistor of an embedded memory
08/20/2002US6436758 Method for forming storage node contact plug of DRAM (dynamic random access memory)
08/20/2002US6436757 Method for fabricating a capacitor having a tantalum oxide dielectrics in a semiconductor device
08/20/2002US6436756 Semiconductor device and fabrication method thereof
08/20/2002US6436755 Dynamic random access memory cell and method for fabricating the same
08/20/2002US6436754 Selective salicide process by reformation of silicon nitride sidewall spacers
08/20/2002US6436753 Semiconductor integrated circuit and method for manufacturing the same
08/20/2002US6436752 Fabrication process is formed of a germanium-silicon alloy. the germanium-silicon alloy may include a first portion of germanium and a second portion of silicon, wherein x is greater than about 0.2.
08/20/2002US6436751 Fabrication method and structure of a flash memory
08/20/2002US6436750 Method of fabricating integrated circuits having transistors and further semiconductor elements
08/20/2002US6436749 Method for forming mixed high voltage (HV/LV) transistors for CMOS devices using controlled gate depletion
08/20/2002US6436748 Method for fabricating CMOS transistors having matching characteristics and apparatus formed thereby
08/20/2002US6436747 Method of fabricating semiconductor device
08/20/2002US6436746 Transistor having an improved gate structure and method of construction
08/20/2002US6436745 Amorphous silicon film using a catalytic metal element promoting crystallization of silicon to form a crystalline first silicon film;
08/20/2002US6436744 Method and structure for creating high density buried contact for use with SOI processes for high performance logic
08/20/2002US6436743 Method of preventing electrical shorts
08/20/2002US6436742 Method for fabricating a thin film transistor with silicon oxynitride film and silicon nitride channel passivation film for preventing a back channel effect
08/20/2002US6436741 Semiconductor integrated circuit device
08/20/2002US6436740 Tri-layer process for forming TFT matrix of LCD with reduced masking steps
08/20/2002US6436737 Method for reducing soft error rates in semiconductor devices
08/20/2002US6436735 Method for mounting an integrated circuit having reduced thermal stresses between a bond pad and a metallic contact
08/20/2002US6436734 Method of making a support circuit for a semiconductor chip assembly
08/20/2002US6436733 Bonding layer method in a semiconductor device
08/20/2002US6436732 Apparatus for applying viscous materials to a lead frame
08/20/2002US6436731 Connecting semiconductor chip to housing; precleaning
08/20/2002US6436730 Microelectronic package comprising tin copper solder bump interconnections and method for forming same
08/20/2002US6436729 Process for producing solid image pickup device and solid image pickup device
08/20/2002US6436724 Distorted surface region of the semiconductor wafer enables higher diffusion rates of reaction gas components into the wafer surface and therefore a higher growth rate of a reaction product film and dopes
08/20/2002US6436723 Ozone water containing an oxidation agent having an oxidation-reduction potential of 2v or more is supplied onto a metal compound film such as srruo film or the like, and the metal compound film is etched by oxidation-reduction reaction
08/20/2002US6436612 Method for forming a protection device with slope laterals
08/20/2002US6436611 Semiconductors with grooves for integrated circuits
08/20/2002US6436609 Photolithography and vapor deposition for semiconductors
08/20/2002US6436608 Lithographic method utilizing a phase-shifting mask
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