Patents
Sitemap › H01 - Basic electric elements › H01L - Semiconductor devices; Electric solid state devices not otherwise provided for › H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
Patents for H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof (658,974)
08/2002
08/15/2002US20020110033 Programmable fuse and antifuse and method therefor
08/15/2002US20020110032 Monotonic dynamic-static pseudo-NMOS logic circuit and method of forming a logic gate array
08/15/2002US20020110018 Semiconductor memory device
08/15/2002US20020110017 Voltage generator for semiconductor device
08/15/2002US20020110016 Semiconductor memory device including plurality of global data lines in parallel arrangement with low parasitic capacitance, and fabrication method thereof
08/15/2002US20020110015 Reduced area sense amplifier isolation layout in a dynamic ram architecture
08/15/2002US20020109973 Lead frame and method for fabricating resin-encapsulated semiconductor device using the same
08/15/2002US20020109955 Electrostatic chuck and method of manufacturing the same
08/15/2002US20020109954 Electrostatic chucks and process for producing the same
08/15/2002US20020109850 Exposure apparatus including interferometer system
08/15/2002US20020109828 Mask handling apparatus, lithographic projection apparatus, device manufacturing method and device manufactured thereby
08/15/2002US20020109825 Lithographic apparatus
08/15/2002US20020109824 Exposure apparatus and exposure method
08/15/2002US20020109815 Contact structure
08/15/2002US20020109814 Display element driving apparatus and display using the same
08/15/2002US20020109798 Pixellated devices such as active matrix liquid crystal displays
08/15/2002US20020109797 TFT LCD device having multi-layered pixel electrodes
08/15/2002US20020109796 Metal contact structure and method for thin film transistor array in liquid crystal display
08/15/2002US20020109660 Reflection type display device and electronic device
08/15/2002US20020109590 Bonded structure using reacted borosilicate mixture
08/15/2002US20020109543 Method for reusing resource for designing operational amplifier, layout generating apparatus, and layout generating program
08/15/2002US20020109539 Multi-level non-volatile semiconductor memory device with verify voltages having a smart temperature coefficient
08/15/2002US20020109526 Programmable logic arrays with ultra thin body transistors
08/15/2002US20020109522 Test system and test method of semiconductor device
08/15/2002US20020109521 Electrical method for assessing yield-limiting asperities in silicon-on-insulator wafers
08/15/2002US20020109514 Planarizing interposer
08/15/2002US20020109437 System for damping oscillations
08/15/2002US20020109242 Semiconductor device and a method of manufacturing the same
08/15/2002US20020109241 Molded flip chip package
08/15/2002US20020109239 Semiconductor device capable of preventing solder balls from being removed in reinforcing pad
08/15/2002US20020109238 Pitch compensation in flip-chip packaging
08/15/2002US20020109237 Semiconductor device and method for making the same
08/15/2002US20020109236 Three-dimensional multi-chip package having chip selection pads and manufacturing method thereof
08/15/2002US20020109235 Enhanced barrier liner formation for vias
08/15/2002US20020109234 Semiconductor device having multi-layer copper line and method of forming the same
08/15/2002US20020109233 Process for providing seed layers for integrated circuit metallurgy
08/15/2002US20020109232 Chip structure and process for forming the same
08/15/2002US20020109231 Composite structure of storage node and method of fabrication thereof
08/15/2002US20020109230 Highly linear integrated resistive contact
08/15/2002US20020109229 Semiconductor device with improved metal interconnection and method for forming the metal interconnection
08/15/2002US20020109228 Bilayer wafer-level underfill
08/15/2002US20020109227 Metal bump
08/15/2002US20020109225 Method for mounting a semiconductor chip on a substrate and semiconductor device adapted for mounting on a substrate
08/15/2002US20020109223 High-frequency integrated circuit and high-frequency circuit device using the same
08/15/2002US20020109219 Semiconductor package with heat sink having air vent
08/15/2002US20020109218 Method and apparatus for packaging flip chip bare die on printed circuit boards
08/15/2002US20020109217 Apparatus for die bonding
08/15/2002US20020109215 Semiconductor device
08/15/2002US20020109214 Leadframe, resin-molded semiconductor device including the leadframe, method of making the leadframe and method for manufacturing the device
08/15/2002US20020109213 Methods of making microelectronic assemblies including compliant interfaces
08/15/2002US20020109208 Method of forming an NPN device
08/15/2002US20020109207 Deep reactive ion etching process and microelectromechanical devices formed thereby
08/15/2002US20020109206 Lateral PNP-type transistor based on a vertical NPN-structure and process for producing such PNP-type transistor
08/15/2002US20020109205 Semiconductor device, method of creating pattern of the same, method of manufacturing the same, and apparatus for creating pattern of the same
08/15/2002US20020109201 Rectifying device and method of fabrication thereof
08/15/2002US20020109199 Transistor devices
08/15/2002US20020109198 Metal oxynitride capacitor barrier layer
08/15/2002US20020109197 Semiconductor device and method for its manufacture
08/15/2002US20020109196 Semiconductor device and its manufacturing method
08/15/2002US20020109195 Semiconductor device with multiple emitter contact plugs
08/15/2002US20020109194 Semiconductor device
08/15/2002US20020109188 Semiconductor device with an isolated zone and corresponding fabrication process
08/15/2002US20020109187 Semiconductor device and method of manufacturing the same
08/15/2002US20020109186 Semiconductor device
08/15/2002US20020109185 Semiconductor device and method of manufacturing thereof
08/15/2002US20020109184 LDMOS with improved safe operating area
08/15/2002US20020109183 Field-effect semiconductor device
08/15/2002US20020109182 Integrated circuit devices having active regions with expanded effective widths and methods of manufacturing same
08/15/2002US20020109181 Method to increase coupling ratio of source to floating gate in split-gate flash
08/15/2002US20020109180 Nonvolatile semiconductor memory device and method of manufacturing the same
08/15/2002US20020109179 Self-aligned non-volatile random access memory cell and process to make the same
08/15/2002US20020109178 Thin film capacitors on silicon germanium substrate and process for making the same
08/15/2002US20020109177 Reduced 1/f noise in MOSFETs
08/15/2002US20020109176 Open bit line dram with ultra thin body transistors
08/15/2002US20020109175 Semiconductor device
08/15/2002US20020109174 Pull-down transistor
08/15/2002US20020109173 Folded bit line DRAM with ultra thin body transistors
08/15/2002US20020109172 Nonvolatile magnetic storage device
08/15/2002US20020109171 Method of forming semiconductor memory device using a double layered capping pattern
08/15/2002US20020109170 Double sided container capacitor for DRAM cell array and method of forming same
08/15/2002US20020109169 Capacitor of a DRAM having a wall protection structure
08/15/2002US20020109168 Ferroelectric memory device and method of forming the same
08/15/2002US20020109167 Memory device and method of fabrication thereof
08/15/2002US20020109166 MFMOS/MFMS non-volatile memory transistors and method of making same
08/15/2002US20020109165 Semiconductor device, manufacturing method thereof, and electronic apparatus
08/15/2002US20020109163 Flash memory with ultra thin vertical body transistors
08/15/2002US20020109162 Reduction of shorts among electrical cells formed on a semiconductor substrate
08/15/2002US20020109159 Method for producing water for use in manufacturing semiconductors
08/15/2002US20020109158 Dynamic memory based on single electron storage
08/15/2002US20020109156 Semiconductor device having signal line above main ground or main VDD line, and manufacturing method thereof
08/15/2002US20020109155 Dram cell and method of manufacturing the same
08/15/2002US20020109150 Semiconductor device and manufacturing method thereof
08/15/2002US20020109146 Nitride-based semiconductor light-emitting device
08/15/2002US20020109144 Method of manufacturing a semiconductor device
08/15/2002US20020109143 Display device and manufacturing method for the same
08/15/2002US20020109142 Non-volatile memory device and manufacturing method thereof
08/15/2002US20020109140 Semiconductor structure and fabrication method
08/15/2002US20020109139 Method for the manufacture of semiconductor devices and circuits
08/15/2002US20020109138 Programmable memory address and decode circuits with ultra thin vertical body transistors
08/15/2002US20020109135 MOS field-effect transistor comprising layered structure including Si layer and SiGe layer OR SiGeC layer as channel regions
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