Patents
Sitemap › H01 - Basic electric elements › H01L - Semiconductor devices; Electric solid state devices not otherwise provided for › H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
Patents for H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof (658,974)
08/2002
08/08/2002WO2001035051A9 X-ray tomography bga (ball grid array) inspections
08/08/2002WO2001035041A9 Method for rapid thermal processing of substrates
08/08/2002WO2001027695A9 Removable cover for protecting a reticle, system including and method of using the same
08/08/2002WO2001022482A9 Method of producing relaxed silicon germanium layers
08/08/2002WO2000067289A9 Apparatus and method for reducing charge accumulation on a substrate
08/08/2002US20020108098 Method for correcting optical proximity effects
08/08/2002US20020108056 Semiconductor device including function verification capability
08/08/2002US20020107675 Wiring failure analysis method using simulation of electromigration
08/08/2002US20020107660 Methods and systems for determining a critical dimension and a thin film characteristic of a specimen
08/08/2002US20020107650 Methods and systems for determining a critical dimension and a presence of defects on a specimen
08/08/2002US20020107611 Feeding robot and control method therefor
08/08/2002US20020107603 Method of efficiently laser marking singulated semiconductor devices
08/08/2002US20020107599 Method and system for dispatching semiconductor lots to manufacturing equipment for fabrication
08/08/2002US20020107160 Contacting a substrate with ozone and a fluorinated solvent selected from linear, branched, cyclic, acyclic, fully or partially fluorinated hydrocarbons
08/08/2002US20020107155 Method and chemistry for cleaning of oxidized copper during chemical mechanical polishing
08/08/2002US20020106980 Abrasive article suitable for modifying a semiconductor wafer
08/08/2002US20020106977 Fixed-abrasive chemical-mechanical planarization of titanium nitride
08/08/2002US20020106976 Method and chemistry for cleaning of oxidized copper during chemical mechanical polishing
08/08/2002US20020106975 Fixed-abrasive chemical-mechanical planarization of titanium nitride
08/08/2002US20020106972 Support and alignment device for enabling chemical mechanical polishing rinse and film measurements
08/08/2002US20020106909 Silicon nitride film forming method, silicon nitride film forming system and silicon nitride film forming system precleaning method
08/08/2002US20020106908 Precleaning process for metal plug that minimizes damage to low-kappa dielectric
08/08/2002US20020106907 Method of forming a conformal oxide film
08/08/2002US20020106906 Method for forming a liner in a trench
08/08/2002US20020106905 Method for removing copper from a wafer edge
08/08/2002US20020106904 Etching method
08/08/2002US20020106903 Manufacturing method of semiconductor device
08/08/2002US20020106902 Etching process for organic anti-reflective coating
08/08/2002US20020106901 Method for forming semiconductor device having high-density contacts
08/08/2002US20020106900 Polishing slurry for the chemical-mechanical polishing of metal and dielectric structures
08/08/2002US20020106899 Method for applying uniform pressurized film across wafer
08/08/2002US20020106898 Methods for removing silicon-oxy-nitride layer and wafer surface cleaning
08/08/2002US20020106897 Polishing of metal substrates
08/08/2002US20020106896 Batch processing for semiconductor wafers to form aluminum nitride and titanium aluminum nitride
08/08/2002US20020106895 Method for forming copper interconnect and enhancing electromigration resistance
08/08/2002US20020106894 Comprises chiral, nonracemic gamma-lactone tail
08/08/2002US20020106893 Structure and process for multi-chip chip attach with reduced risk of electrostatic discharge damage
08/08/2002US20020106892 Method for manufacturing semiconductor device
08/08/2002US20020106891 Method of fabricating semiconductor devices having low dielectric interlayer insulation layer
08/08/2002US20020106890 Method for multilevel copper interconnects for ultra large scale integration
08/08/2002US20020106889 Slot via filled dual damascene structure without middle stop layer and method for making the same
08/08/2002US20020106888 Process for manufacturing an electronic semiconductor device with improved insulation by means of air gaps
08/08/2002US20020106887 Method of forming a dual damascene structure by patterning a sacrificial layer to define the plug portions of the structure
08/08/2002US20020106886 Planarized semiconductor interconnect topography and method for polishing a metal layer to form interconnect
08/08/2002US20020106885 Method of fabricating a slot dual damascene structure without middle stop layer
08/08/2002US20020106884 Method for multilevel copper interconnects for ultra large scale integration
08/08/2002US20020106883 Solder bump transfer sheet, method for producing the same, and methods for fabricating semiconductor device and printed board
08/08/2002US20020106882 Method of producing a semiconductor layer on a substrate
08/08/2002US20020106881 Prevention of contact failure by hydrogen treatment
08/08/2002US20020106880 Method for avoiding the junction leakage
08/08/2002US20020106879 Metallization structures for semiconductor device interconnects, methods for making same, and semiconductor devices including same
08/08/2002US20020106877 Method of fabricating a damascene structure
08/08/2002US20020106876 Method of forming a buffer layer over a polysilicon gate
08/08/2002US20020106875 Method for manufacturing and structure for transistors with reduced gate to contact spacing
08/08/2002US20020106874 Crystal growth process, semiconductor device, and its production process
08/08/2002US20020106872 Post-epitaxial thermal oxidation for reducing microsteps on polished semiconductor wafersost epitaxial thermal oxidation
08/08/2002US20020106871 Optical membrane singulation process utilizing backside and frontside protective coating during die saw
08/08/2002US20020106870 Controlled cleaving process
08/08/2002US20020106869 Separating machine for thinned semiconductor substrate and separation method
08/08/2002US20020106868 Protecting method for semiconductor wafer and surface protecting adhesive film for semiconductor wafer used said method
08/08/2002US20020106867 Wafer-level transfer of membranes in semiconductor processing
08/08/2002US20020106866 Self-aligned source pocket for flash memory cells
08/08/2002US20020106865 Method of forming shallow trench isolation
08/08/2002US20020106864 Method for filling of a shallow trench isolation
08/08/2002US20020106863 Method for fabricating semiconductor devices
08/08/2002US20020106862 Glass frit wafer bonding process and packages formed thereby
08/08/2002US20020106861 Method of manufacturing a semiconductor film and method of manufacturing a semiconductor device
08/08/2002US20020106860 Semiconductor device and method of manufacturing the same
08/08/2002US20020106859 Method of fabricating nonvolatile semiconductor memory device
08/08/2002US20020106858 Work function tuning for MOSFET gate electrodes
08/08/2002US20020106857 Method for surface area enhancement of capacitors by film growth and self masking
08/08/2002US20020106856 Method for forming a storage node of a capacitor
08/08/2002US20020106855 Method of manufacturing semiconductor device
08/08/2002US20020106854 Semiconductor memory device and method of producing the same
08/08/2002US20020106853 Method of reducing oxygen vacancies in a high k capacitor dielectric region, and DRAM processing methods
08/08/2002US20020106852 Lowered channel doping with source side boron implant for deep sub 0.18 micron flash memory cell
08/08/2002US20020106851 Cell based integrated circuit and unit cell architecture therefor
08/08/2002US20020106850 Method of fabricating deep sub-micron CMOS source/drain with MDD and selective CVD silicide
08/08/2002US20020106847 Fabrication of electronic circuit elements using unpatterned semiconductor layers
08/08/2002US20020106846 Formation of a tantalum-nitride layer
08/08/2002US20020106845 Method for rounding corners and removing damaged outer surfaces of a trench
08/08/2002US20020106844 Method for manufacturing semiconductor device
08/08/2002US20020106843 Array substrate for display, method of manufacturing array substrate for display and display device using the array substrate
08/08/2002US20020106842 Methods for growth of relatively large step-free sic crystal surfaces
08/08/2002US20020106841 Method of manufacturing semiconductor device
08/08/2002US20020106840 Thin film transistor-liquid crystal display and manufacturing method therefor
08/08/2002US20020106839 Thin film transistor and method for manufacturing the same
08/08/2002US20020106837 Method of generating integrated circuit feature layout for improved chemical mechanical polishing
08/08/2002US20020106836 Semiconductor device and a method of manufacturing the same
08/08/2002US20020106833 Semiconductor device and method for fabricating same
08/08/2002US20020106832 Method and apparatus for attaching solder members to a substrate
08/08/2002US20020106831 Method for laminating and mounting semiconductor chip
08/08/2002US20020106830 Process for producing optical article
08/08/2002US20020106826 Susceptorless reactor for growing epitaxial layers on wafers by chemical vapor deposition
08/08/2002US20020106825 Method for manufacturing a liquid crystal display
08/08/2002US20020106820 Device and method for nondestructive inspection on semiconductor device
08/08/2002US20020106819 Structure evaluating method, method for manufacturing semiconductor devices, and recording medium
08/08/2002US20020106818 Method of manufacturing semiconductor device and apparatus of automatically adjusting semiconductor pattern
08/08/2002US20020106817 Semiconductor test apparatus, and method of testing semiconductor device
08/08/2002US20020106816 Method for fabricating semiconductor device
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