Patents
Sitemap › H01 - Basic electric elements › H01L - Semiconductor devices; Electric solid state devices not otherwise provided for › H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
Patents for H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof (658,974)
08/2002
08/15/2002US20020111020 Application of controlling gas valves to reduce particles from CVD process
08/15/2002US20020111019 Method and an apparatus to electroless plate a metal layer while eliminating the photoelectric effect
08/15/2002US20020111018 Method for forming metal silicide layer
08/15/2002US20020111017 Pre-pattern surface modification for low-k dielectrics using A H2 plasma
08/15/2002US20020111016 Method and apparatus for injection molded flip chip encapsulation
08/15/2002US20020111015 Method of forming metal connection elements in integrated circuits
08/15/2002US20020111014 Planarization method of inter-layer dielectrics and inter-metal dielectrics
08/15/2002US20020111013 Method for formation of single inlaid structures
08/15/2002US20020111012 Partially-overlapped interconnect structure and method of making
08/15/2002US20020111011 Method for forming a contact plug without a dimple surface
08/15/2002US20020111010 Common ball-limiting metallurgy for I/O sites
08/15/2002US20020111009 Reliable metal bumps on top of I/O pads after removal of test probe marks
08/15/2002US20020111007 Semiconductor package and fabricating method thereof
08/15/2002US20020111006 Method for forming landing pad
08/15/2002US20020111005 Method of forming a contact pad
08/15/2002US20020111004 Semiconductor device having a fuse and a fabrication process thereof
08/15/2002US20020111003 Stereolithographically fabricated conductive elements, semiconductor device components and assemblies including such conductive elements, and methods
08/15/2002US20020111002 Method of selectively forming silicide film of merged dram and logic
08/15/2002US20020111001 Formation of metal oxide gate dielectric
08/15/2002US20020111000 Semiconductor manufacturing apparatus
08/15/2002US20020110999 Reliable interconnects with low via/contact resistance
08/15/2002US20020110998 Chemical vapor deposition method
08/15/2002US20020110997 Methods of fabricating gallium nitride semiconductor layers on substrates including non-gallium nitride posts
08/15/2002US20020110995 Use of discrete chemical mechanical polishing processes to form a trench isolation region
08/15/2002US20020110994 Method for forming trench type isolation film using annealing
08/15/2002US20020110993 Method for forming an electrode with a layer of hemispherical grains thereon
08/15/2002US20020110992 Use of hydrocarbon addition for the elimination of micromasking during etching
08/15/2002US20020110991 Sequential pulse deposition
08/15/2002US20020110990 Semiconductor device fabrication method
08/15/2002US20020110989 Semiconductor device, method of manufacturing same and method of designing same
08/15/2002US20020110988 Front stage process of a fully depleted silicon-on-insulator device and a structure thereof
08/15/2002US20020110987 Method of forming a metal to polysilicon contact in oxygen environment
08/15/2002US20020110986 Dual doped gates
08/15/2002US20020110985 Methid of making a single transistor non-volatile memory device
08/15/2002US20020110984 Method of fabricating a trenched flash memory cell
08/15/2002US20020110983 Method of fabricating a split-gate flash memory cell
08/15/2002US20020110982 Method for fabricating a semiconductor device
08/15/2002US20020110981 Method for fabricating a semiconductor device
08/15/2002US20020110980 Method for forming capacitor of a dram having a wall protection structure
08/15/2002US20020110979 Method for forming a dram contact plug
08/15/2002US20020110978 Method for treating the surface of a bit line conductive layer
08/15/2002US20020110977 Semiconductor device having concave electrode and convex electrode and method of manufacturing thereof
08/15/2002US20020110976 Dram memory integration method
08/15/2002US20020110975 Capacitors, DRAM arrays, monolithic integrated circuits, and methods of forming capacitors, DRAM arrays, and monolithic integrated circuits
08/15/2002US20020110974 Dynamic memory based on single electron storage
08/15/2002US20020110973 Fabrication method and structure of a flash memory
08/15/2002US20020110972 Implant method for forming Si3N4 spacer
08/15/2002US20020110971 Semiconductor memory device with trench-type stacked cell capacitors and method for manufacturing the same
08/15/2002US20020110970 Method of fabricating trench capacitor of a memory cell
08/15/2002US20020110969 Semiconductor device and method for manufacturing the same
08/15/2002US20020110968 Semiconductor device fabricating method
08/15/2002US20020110967 Method of forming metal lines in an integrated circuit using hard mask spacers
08/15/2002US20020110966 Semiconductor device having multi-layered spacer and method of manufacturing the same
08/15/2002US20020110965 Semiconductor device and fabrication method thereof
08/15/2002US20020110964 Recrystallization method of polysilicon film in thin film transistor
08/15/2002US20020110963 Thin-film transistor substrate, liquid crystal display unit and manufacturing method of thin-film transistor substrate
08/15/2002US20020110962 System for manufacturing a thin-film transistor, method of manufacturing a thin-film transistor, method of evaluating polysilicon, and apparatus for inspecting polysilicon
08/15/2002US20020110961 Method to prevent an ITO from opening
08/15/2002US20020110960 Thin film transistor assembly, particularly suitable for liquid crystal display device, and process for fabricating the same
08/15/2002US20020110959 Semiconductor device layout
08/15/2002US20020110956 Chip lead frames
08/15/2002US20020110955 Electronic device including at least one chip fixed to a support and a method for manufacturing such a device
08/15/2002US20020110954 Semiconductor device and method of fabricating same
08/15/2002US20020110953 Wafer on wafer packaging and method of fabrication for full-wafer burn-in and testing
08/15/2002US20020110952 Multiple-function electronic chip
08/15/2002US20020110950 Method of fabricating a light receiving device
08/15/2002US20020110949 Charge-coupled device wafer cover plate with compact interconnect wiring
08/15/2002US20020110947 Semiconductor light emitting element and its manufacturing method
08/15/2002US20020110946 Metamorphic long wavelength high-speed photodiode
08/15/2002US20020110945 Optical semiconductor device having an epitaxial layer of iii-v compound semiconductor material containing n as a group v element
08/15/2002US20020110943 6699733 not granted per USPTO
08/15/2002US20020110942 System and method for prototyping and fabricating complex microwave circuits
08/15/2002US20020110941 Semiconductor device and manufacturing method thereof
08/15/2002US20020110938 Measurement and analysis of mercury-based pseudo-field effect transistors
08/15/2002US20020110936 Inductor recognition method, layout inspection method, computer readable recording medium in which a layout inspection program is recorded and process for a semiconductor device
08/15/2002US20020110935 Method for fabricating a ferroelectric memory configuration
08/15/2002US20020110934 Rapid- temperature pulsing anneal method at low temperature for fabricating layered superlattice materials and making electronic devices including same
08/15/2002US20020110770 Cooling system for reducing particles pollution
08/15/2002US20020110769 Heat treatment method and heat treatment apparatus
08/15/2002US20020110761 Photolithography patterns
08/15/2002US20020110757 Low cost integrated out-of-plane micro-device structures and method of making
08/15/2002US20020110750 Positive-working photoresist composition
08/15/2002US20020110742 Method for correcting design pattern of semiconductor circuit, a photomask fabricated using the corrected design pattern data, a method for inspecting the photomask and a method for generating pattern data for inspection of photomask
08/15/2002US20020110741 Phase shift mask blank, photo mask blank and manufacturing apparatus and method of blanks
08/15/2002US20020110709 Material of low volume resistivity, an aluminum nitride sintered body and a member used for the production of semiconductors
08/15/2002US20020110703 Striped lower electrodes on an insulating substrate, amorphous carbon is filled between them; organic thin film layers formed on filler and lower electrodes, and striped upper electrodes are formed along a second direction
08/15/2002US20020110665 Aperture fill
08/15/2002US20020110661 Abrasive molding and abrasive disc provided with same
08/15/2002US20020110648 Diamond film depositing apparatus and method thereof
08/15/2002US20020110641 Nozzle which drops the coating liquid on the center of substrate includes spiral groove or fins for creating gyration to the dropped coating
08/15/2002US20020110640 Coating method and apparatus for semiconductor process
08/15/2002US20020110637 Substrate is coated with electroconductive film and subjected to baking; integrated circuits
08/15/2002US20020110449 Method of manipulating wafers
08/15/2002US20020110309 Monolithic integrated optical component including a modulator and a heterojunction bipolar transistor
08/15/2002US20020110270 Nonlot based method for assembling integrated circuit devices
08/15/2002US20020110217 X-ray illumination optical system and X-ray reduction exposure apparatus
08/15/2002US20020110209 Transmission circuit and semiconductor device
08/15/2002US20020110041 Semiconductor memory device with improved setup time and hold time
08/15/2002US20020110039 Memory address and decode circuits with ultra thin body transistors
08/15/2002US20020110036 Static memory cell having independent data holding voltage
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