| Patents for H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof (658,974) |
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| 08/27/2002 | US6441489 Semiconductor device with tantalum nitride barrier film |
| 08/27/2002 | US6441488 Fan-out translator for a semiconductor package |
| 08/27/2002 | US6441487 Chip scale package using large ductile solder balls |
| 08/27/2002 | US6441486 BGA substrate via structure |
| 08/27/2002 | US6441485 Apparatus for electrically mounting an electronic device to a substrate without soldering |
| 08/27/2002 | US6441484 Semiconductor device having switching elements around a central control circuit |
| 08/27/2002 | US6441478 Semiconductor package having metal-pattern bonding and method of fabricating the same |
| 08/27/2002 | US6441475 Chip scale surface mount package for semiconductor device and process of fabricating the same |
| 08/27/2002 | US6441474 Semiconductor device and liquid crystal module adopting the same |
| 08/27/2002 | US6441473 Flip chip semiconductor device |
| 08/27/2002 | US6441469 Semiconductor memory configuration with dummy components on continuous diffusion regions |
| 08/27/2002 | US6441468 Semiconductor device |
| 08/27/2002 | US6441467 Semiconductor device having active element connected to an electrode metal pad via a barrier metal layer and interlayer insulating film |
| 08/27/2002 | US6441466 Method and apparatus for reducing fixed charge in semiconductor device layers |
| 08/27/2002 | US6441465 Scribe line structure for preventing from damages thereof induced during fabrication |
| 08/27/2002 | US6441464 Gate oxide stabilization by means of germanium components in gate conductor |
| 08/27/2002 | US6441463 IGBT, control circuit, and protection circuit on same substrate |
| 08/27/2002 | US6441462 Self-aligned SiGe NPN with improved ESD robustness using wide emitter polysilicon extension |
| 08/27/2002 | US6441461 Thin film resistor with stress compensation |
| 08/27/2002 | US6441457 Fuse in semiconductor device and fabricating method thereof |
| 08/27/2002 | US6441456 Semiconductor device and a process for manufacturing the same |
| 08/27/2002 | US6441452 Method of reducing defects in anti-reflective coatings and semiconductor structures fabricated thereby |
| 08/27/2002 | US6441448 Semiconductor storage device |
| 08/27/2002 | US6441447 Co-patterning thin-film resistors of different compositions with a conductive hard mask and method for same |
| 08/27/2002 | US6441445 Integrated device with bipolar transistor and electronic switch in “emitter switching” configuration |
| 08/27/2002 | US6441444 Semiconductor device having a nitride barrier for preventing formation of structural defects |
| 08/27/2002 | US6441442 Integrated inductive circuits |
| 08/27/2002 | US6441441 Semiconductor device and method of manufacturing the same |
| 08/27/2002 | US6441440 Semiconductor device and circuit having low tolerance to ionizing radiation |
| 08/27/2002 | US6441437 Integrated semiconductor circuit with protective structure for protection against electrostatic discharge |
| 08/27/2002 | US6441436 SOI device and method of fabrication |
| 08/27/2002 | US6441435 SOI device with wrap-around contact to underside of body, and method of making |
| 08/27/2002 | US6441434 Semiconductor-on-insulator body-source contact and method |
| 08/27/2002 | US6441433 Method of making a multi-thickness silicide SOI device |
| 08/27/2002 | US6441431 Lateral double diffused metal oxide semiconductor device |
| 08/27/2002 | US6441430 Semiconductor device with floating gates |
| 08/27/2002 | US6441429 Split-gate flash memory device having floating gate electrode with sharp peak |
| 08/27/2002 | US6441427 NOR-type flash memory and method for manufacturing the same |
| 08/27/2002 | US6441426 Nonvolatile semiconductor memory device and method of manufacturing the same |
| 08/27/2002 | US6441425 Non-volatile semiconductor device and non-volatile semiconductor memory device for storing multi-value information |
| 08/27/2002 | US6441424 Integrated circuit configuration having at least one capacitor and method for producing the same |
| 08/27/2002 | US6441423 Trench capacitor with an intrinsically balanced field across the dielectric |
| 08/27/2002 | US6441422 Structure and method for ultra-scalable hybrid DRAM cell with contacted P-well |
| 08/27/2002 | US6441421 High dielectric constant materials forming components of DRAM storage cells |
| 08/27/2002 | US6441420 Semiconductor device and method of fabricating the same |
| 08/27/2002 | US6441419 Encapsulated-metal vertical-interdigitated capacitor and damascene method of manufacturing same |
| 08/27/2002 | US6441418 Spacer narrowed, dual width contact for charge gain reduction |
| 08/27/2002 | US6441417 Single c-axis PGO thin film on ZrO2 for non-volatile memory applications and methods of making the same |
| 08/27/2002 | US6441415 Ferroelectric and paraelectric thin film devices using dopants which eliminate ferroelectricity |
| 08/27/2002 | US6441414 Ferroelectric field effect transistor, memory utilizing same, and method of operating same |
| 08/27/2002 | US6441410 MOSFET with lateral resistor ballasting |
| 08/27/2002 | US6441400 Semiconductor device and method of fabricating the same |
| 08/27/2002 | US6441399 Semiconductor integrated system |
| 08/27/2002 | US6441398 Algorithm for detecting sloped contact holes using a critical-dimension waveform |
| 08/27/2002 | US6441397 Evaluation of semiconductor chargeup damage and apparatus therefor |
| 08/27/2002 | US6441396 In-line electrical monitor for measuring mechanical stress at the device level on a semiconductor wafer |
| 08/27/2002 | US6441395 Column-row addressable electric microswitch arrays and sensor matrices employing them |
| 08/27/2002 | US6441393 Semiconductor devices with selectively doped III-V nitride layers |
| 08/27/2002 | US6441392 Device based on quantic islands and method for making same |
| 08/27/2002 | US6441391 Semiconductor device having drain and gate electrodes formed to lie along few degrees of direction in relation to the substrate |
| 08/27/2002 | US6441383 Charged particle beam lithography apparatus for forming pattern on semi-conductor |
| 08/27/2002 | US6441351 Heating device, method for evaluating heating device and pattern forming method |
| 08/27/2002 | US6441350 Temperature control system for a thermal reactor |
| 08/27/2002 | US6441349 System for facilitating uniform heating temperature of photoresist |
| 08/27/2002 | US6441320 Electrically conductive projections having conductive coverings |
| 08/27/2002 | US6441316 Printed-circuit board and a semiconductor module, and a manufacturing process of the semiconductor module |
| 08/27/2002 | US6441297 Solar cell arrangement |
| 08/27/2002 | US6441072 High-melting polyamide composition for electronic applications |
| 08/27/2002 | US6440879 Physical vapor deposition apparatus with modified shutter disk and cover ring |
| 08/27/2002 | US6440878 Plasma enhanced chemical vapor deposition (pecvd) process is provided for depositing one or more dielectric material layers on a substrate for use in interconnect structures of integrated circuits |
| 08/27/2002 | US6440876 Low-K dielectric constant CVD precursors formed of cyclic siloxanes having in-ring SI—O—C, and uses thereof |
| 08/27/2002 | US6440875 Masking layer method for forming a spacer layer with enhanced linewidth control |
| 08/27/2002 | US6440874 High throughput plasma resist strip process for temperature sensitive applications |
| 08/27/2002 | US6440873 Post metal etch cleaning method |
| 08/27/2002 | US6440872 Method for hybrid DRAM cell utilizing confined strap isolation |
| 08/27/2002 | US6440871 Layer of ozonated water on the photoresist; directing at least one gas other than ozone toward the semiconductor device so as to move said layer of ozonated water across the photoresist; nitrogen, air, and gaseous hydrochloric acid |
| 08/27/2002 | US6440870 Accuracy control of etching using plasma |
| 08/27/2002 | US6440869 Method of forming the capacitor with HSG in DRAM |
| 08/27/2002 | US6440868 Metal gate with CVD amorphous silicon layer and silicide for CMOS devices and method of making with a replacement gate process |
| 08/27/2002 | US6440867 Metal gate with PVD amorphous silicon and silicide for CMOS devices and method of making the same with a replacement gate process |
| 08/27/2002 | US6440866 Plasma reactor with heated source of a polymer-hardening precursor material |
| 08/27/2002 | US6440865 Metal layer with an antireflection layer |
| 08/27/2002 | US6440864 Substrate cleaning process |
| 08/27/2002 | US6440863 Within microelectronics fabrications. |
| 08/27/2002 | US6440862 Stepped photoresist profile and opening formed using the profile |
| 08/27/2002 | US6440861 Method of forming dual damascene structure |
| 08/27/2002 | US6440860 Semiconductor processing methods of transferring patterns from patterned photoresists to materials, and structures comprising silicon nitride |
| 08/27/2002 | US6440859 Method for etching passivation layer of wafer |
| 08/27/2002 | US6440858 Multi-layer hard mask for deep trench silicon etch |
| 08/27/2002 | US6440857 Planarizing a wafer surface of aluminum and a ti/tin barrier layer; undesired surface nonplanarity after the cmp process, such as metal dishing and corrosion of dielectric layers with complicated pattern geometry, can be avoided |
| 08/27/2002 | US6440856 Cleaning agent for semiconductor parts and method for cleaning semiconductor parts |
| 08/27/2002 | US6440855 Method of processing surface of workpiece and method of forming semiconductor thin layer |
| 08/27/2002 | US6440854 Deposited by physical vapor deposition |
| 08/27/2002 | US6440853 Integrated circuit |
| 08/27/2002 | US6440852 Integrated circuit including passivated copper interconnection lines and associated manufacturing methods |
| 08/27/2002 | US6440851 Method and structure for controlling the interface roughness of cobalt disilicide |
| 08/27/2002 | US6440849 Substantially eliminates the grain growth of copper due to self annealing; |
| 08/27/2002 | US6440848 Low resistance. |
| 08/27/2002 | US6440847 Method for forming a via and interconnect in dual damascene |
| 08/27/2002 | US6440846 Method for forming semiconductor device |