| Patents for G11C 8 - Arrangements for selecting an address in a digital store (19,368) |
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| 08/14/2001 | US6275442 Address decoder and method for ITS accelerated stress testing |
| 08/09/2001 | WO2001058071A1 Memory circuit, and synchronous detection circuit |
| 08/09/2001 | WO2001057874A2 Voltage boost level clamping circuit for a flash memory |
| 08/09/2001 | WO2001057873A1 Integrated semiconductor memory and method for resetting memory cells of an integrated semiconductor memory |
| 08/09/2001 | US20010011987 Shift register circuit capable of reducing consumption of power with reduced capacitive load of clock signal line and image display device including it |
| 08/09/2001 | DE10004109A1 Memory module of electronic data processor, has switch connecting main and local data lines, arranged such that delay time of bit during synchronous memory access is made shorter |
| 08/08/2001 | EP1122887A1 Pre-charging circuit of an output buffer |
| 08/08/2001 | EP1122740A1 Integrated semiconductor memory and method for clearing memory cells of an integrated semiconductor memory |
| 08/08/2001 | EP1122739A2 Accelerated carry generation. |
| 08/08/2001 | EP1122737A1 Circuit for managing the transfer of data streams from a plurality of sources within a system |
| 08/08/2001 | EP1122736A1 ATD generation in a synchronous memory |
| 08/08/2001 | EP1122735A1 Interleaved data path and output management architecture for an interleaved memory and load pulser circuit for outputting the read data |
| 08/08/2001 | EP1122734A1 Burst interleaved memory with burst mode access in synchronous read phases wherein the two sub-arrays are independently readable with random access during asynchronous read phases |
| 08/08/2001 | EP1122733A1 Internal regeneration of the address latch enable (ALE) signal of a protocol of management of a burst interleaved memory and relative circuit |
| 08/08/2001 | CN1307281A Relative allocation device and method for data storage card |
| 08/07/2001 | US6272608 Method and apparatus for synchronous data transfers in a memory device with lookahead logic for detecting latency intervals |
| 08/07/2001 | US6272567 System for interposing a multi-port internally cached DRAM in a control path for temporarily storing multicast start of packet data until such can be passed |
| 08/07/2001 | US6272066 Synchronous semiconductor memory device capable of high speed reading and writing |
| 08/07/2001 | US6272065 Address generating and decoding circuit for use in burst-type random access memory device having a double data rate, and an address generating method thereof |
| 08/07/2001 | US6272063 Semiconductor memory device |
| 08/07/2001 | US6272062 Semiconductor memory with programmable bitline multiplexers |
| 08/07/2001 | US6272055 Semiconductor memory device |
| 08/07/2001 | US6272053 Semiconductor device with common pin for address and data |
| 08/07/2001 | US6272042 Nonvolatile semiconductor memory |
| 08/07/2001 | US6271866 Dual port memory system for buffering asynchronous input to a raster scanned display |
| 08/07/2001 | US6271682 Method and apparatus for high-speed edge-programmable timing signal generator |
| 08/07/2001 | US6271587 Connection arrangement for enbaling the use of identical chips in 3-dimensional stacks of chips requiring address specific to each chip |
| 08/02/2001 | WO2001056160A1 Variable logical circuit, semiconductor integrated circuit, and method for manufacturing semiconductor integrated circuit |
| 08/02/2001 | US20010011353 Secure module with microprocessor and co-processor |
| 08/02/2001 | US20010010656 Sequentially addressing a nonvolatile writeable memory device |
| 08/02/2001 | US20010010655 Method and system for accessing rows in multiple memory banks within an integrated circuit |
| 08/02/2001 | US20010010654 Multiple ports memory-cell structure |
| 08/02/2001 | US20010010650 Semiconductor memory device having operation delay function of column address strobe command, and buffer and signal transmission circuit which are applied to the semiconductor memory device |
| 08/02/2001 | US20010010642 Static random access memory (SRAM) array central global decoder system and method |
| 08/02/2001 | US20010010640 Semiconductor memory device |
| 08/02/2001 | DE19944738C2 Segmentierte Wortleitungsarchitektur zur Aufteilung einer Wortleitung in mehrere Bänke für Zellenfelder mit langen Bitleitungen Segmented wordline architecture for sharing a word line into multiple banks for cell arrays with long bitlines |
| 08/02/2001 | DE10102626A1 Signalübertragungsschaltung, Puffer und zugehöriges Halbleiterspeicherbauelement Signal transmission circuit, buffers and related semiconductor memory device |
| 08/02/2001 | DE10065476A1 Halbleiter-Speicheranordnung und Verfahren für deren Bit-Leitungsverbindung A semiconductor memory device and methods for their bit line connection |
| 08/02/2001 | DE10047176A1 Halbleiterspeicheranordnung, welche mit einer Erzeugungseinrichtung für ein internes Taktsignal für eine spezielle Betriebsart ausgestattet ist A semiconductor memory device, which is equipped with a device for generating an internal clock signal for a particular operating mode |
| 08/01/2001 | EP1119859A2 Dual-port memory location |
| 08/01/2001 | EP1119858A1 Decoder element for producing an output signal with three different potentials and operating method for said decoder element |
| 07/31/2001 | US6269051 Semiconductor device and timing control circuit |
| 07/31/2001 | US6269047 Semiconductor memory device |
| 07/31/2001 | US6269046 Semiconductor memory device having improved decoders for decoding row and column address signals |
| 07/31/2001 | US6269045 Self-timed address decoder for register file and compare circuit of multi-port cam |
| 07/31/2001 | US6269036 System and method for testing multiple port memory devices |
| 07/31/2001 | US6269031 Semiconductor memory device |
| 07/31/2001 | US6268746 Method and apparatus for logic synchronization |
| 07/31/2001 | US6268741 Semiconductor integrated circuits with power reduction mechanism |
| 07/26/2001 | WO2001001450A3 Dram cell fabrication process and method for operating same |
| 07/26/2001 | US20010009536 Relative address allocation apparatus and method for data storage card |
| 07/26/2001 | US20010009532 Semiconductor memory device |
| 07/26/2001 | US20010009531 Memory device having a variable data output length |
| 07/26/2001 | US20010009529 Column select latch for SDRAM |
| 07/26/2001 | US20010009519 Dynamic ram and semiconductor device |
| 07/26/2001 | US20010009518 High voltage boosted word line supply charge pump and regulator for dram |
| 07/26/2001 | US20010009382 Row decoder with switched power supply |
| 07/26/2001 | US20010009276 Memory device having a variable data output length and a programmable register |
| 07/26/2001 | US20010009275 Clock synchronization circuit and semiconductor device having the same |
| 07/25/2001 | EP1119003A2 Address decoder optimization |
| 07/25/2001 | EP1118937A2 Nonvolatile semiconductor memory device having electrically and collectively erasable characteristics |
| 07/25/2001 | EP1118082A1 Quantum random address memory with polymer mixer and/or memory |
| 07/24/2001 | US6266746 Control apparatus for random access memories |
| 07/24/2001 | US6266735 Information processing system |
| 07/24/2001 | US6266293 Semiconductor memory device |
| 07/24/2001 | US6266292 DRAM core refresh with reduced spike current |
| 07/24/2001 | US6266285 Method of operating a memory device having write latency |
| 07/24/2001 | US6266283 Semiconductor memory device |
| 07/24/2001 | US6266264 Word line straps using two different layers of metal |
| 07/19/2001 | WO2001052265A2 Decoder circuit |
| 07/19/2001 | US20010008498 Fast accessible dynamic type semiconductor memory device |
| 07/19/2001 | US20010008497 Semiconductor device |
| 07/19/2001 | US20010008280 Semiconductor integrated circuit |
| 07/19/2001 | DE10063732A1 Halbleiterspeicherbauelement mit hierarchischer Wortleitungsstruktur Semiconductor memory device with a hierarchical word line structure |
| 07/19/2001 | DE10063631A1 Virtual channel synchronized with a dynamic RAM for driving memory cells uses a semiconductor memory device with a base cell structure for a word driver, a main decoder and a reader booster for reading out information from the cells. |
| 07/19/2001 | DE10061604A1 Halbleiterspeicher, der mit einem Reihenadressendecodierer versehen ist, der eine reduzierte Signalausbreitungsverzögerungszeit hat A semiconductor memory, which is provided with a row address decoder, which has a reduced signal propagation delay time |
| 07/18/2001 | EP1116240A1 Wordline driver for flash electrically erasable programmable read only memory (eeprom) |
| 07/18/2001 | EP1116239A1 Simultaneous operation flash memory device with a flexible bank partition architecture |
| 07/18/2001 | EP1116238A1 Bank selector circuit for a simultaneous operation flash memory device with a flexible bank partition architecture |
| 07/18/2001 | EP1116236A1 Method of making flexibly partitioned metal line segments for a simultaneous operation flash memory device with a flexible bank partition architecture |
| 07/18/2001 | CN1068687C Dynamic allocation method for storage with multi-stage voice |
| 07/17/2001 | US6263477 Layout information generating apparatus and method thereof |
| 07/17/2001 | US6262939 Semiconductor integrated circuit device |
| 07/17/2001 | US6262938 Synchronous DRAM having posted CAS latency and method for controlling CAS latency |
| 07/17/2001 | US6262937 Synchronous random access memory having a read/write address bus and process for writing to and reading from the same |
| 07/17/2001 | US6262936 Random access memory having independent read port and write port and process for writing to and reading from the same |
| 07/17/2001 | US6262935 Shift redundancy scheme for wordlines in memory circuits |
| 07/17/2001 | US6262934 Memory circuit including word line reset circuit and method of resetting word line |
| 07/17/2001 | US6262933 High speed programmable address decoder |
| 07/17/2001 | US6262932 RAM cells having a substantially balanced number of N-MOS and P-MOS transistors for improving layout areas |
| 07/17/2001 | US6262931 Semiconductor memory device having voltage down convertor reducing current consumption |
| 07/17/2001 | US6262929 Pre-charging circuit and method for a word match line of a content add ressable memory (CAM) |
| 07/17/2001 | US6262924 Programmable semiconductor memory device |
| 07/17/2001 | US6262918 Space management for managing high capacity nonvolatile memory |
| 07/17/2001 | US6262913 Method and apparatus for improving cell life of sequential counters stored in non-volatile memory |
| 07/17/2001 | US6262912 Single ended simplex dual port memory cell |
| 07/17/2001 | US6262750 Process for storing cues with different formats in a memory and corresponding storage and reading device |
| 07/12/2001 | US20010008006 Method for bus capacitance reduction |
| 07/12/2001 | US20010007776 Signal in response to activation; supply connecting circuits; high speed |
| 07/12/2001 | US20010007539 Semiconductor device |