| Patents for G11C 8 - Arrangements for selecting an address in a digital store (19,368) |
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| 06/27/2002 | US20020079545 High-voltage switching device and application to a non-volatile memory |
| 06/27/2002 | US20020079524 Lower electrode isolation in a double-wide trench |
| 06/27/2002 | DE10061580A1 Speichereinrichtung und Verfahren zu deren Betrieb Memory means and method for its operation |
| 06/26/2002 | EP1217629A1 Analog signal sampling acquisition process and acquisition system therefor |
| 06/26/2002 | CN1355922A Memory array with address scrambling |
| 06/26/2002 | CN1086817C Method for connecting DRAM module to DRAM exchange control system |
| 06/25/2002 | US6412072 Parasitically powered microprocessor capable of transmitting data over a single data line and ground |
| 06/25/2002 | US6412041 Real time processing method of a flash memory |
| 06/25/2002 | US6411561 Semiconductor device including multi-chip |
| 06/25/2002 | US6411560 Semiconductor memory device capable of reducing leakage current flowing into substrate |
| 06/25/2002 | US6411557 Memory architecture with single-port cell and dual-port (read and write) functionality |
| 06/25/2002 | US6411554 High voltage switch circuit having transistors and semiconductor memory device provided with the same |
| 06/25/2002 | US6411546 Nonvolatile memory using flexible erasing methods and method and system for using same |
| 06/25/2002 | US6411140 Method and apparatus for reducing skew between input signals and clock signals within an integrated circuit |
| 06/20/2002 | WO2002049035A2 Memory device and method for the operation of the same |
| 06/20/2002 | WO2002005285A3 Flash memory architecture implementing simultaneously programmable multiple flash memory banks that are host compatible |
| 06/20/2002 | US20020078311 Multi-port memory based on DRAM core |
| 06/20/2002 | US20020075749 Method and apparatus for generating memory addresses for testing memory devices |
| 06/20/2002 | US20020075746 Fast accessible dynamic type semiconductor memory device |
| 06/20/2002 | US20020075745 Power up initialization circuit responding to an input signal |
| 06/20/2002 | US20020075734 Digital memory structure and device, and methods for the management thereof |
| 06/20/2002 | US20020075715 Memory device, method of accessing the memory device, and Reed-Solomon decoder including the memory device |
| 06/20/2002 | US20020075706 Boosted voltage supply |
| 06/20/2002 | US20020075047 Configuration for generating a clock including a delay circuit and method thereof |
| 06/19/2002 | EP1215904A2 Broadcast and reception system, and receiver/decoder and remote controller therefor |
| 06/19/2002 | EP1214713A1 Architecture, method(s) and circuitry for low power memories |
| 06/18/2002 | US6408356 Apparatus and method for modifying signals from a CPU to a memory card |
| 06/18/2002 | US6407963 Semiconductor memory device of DDR configuration having improvement in glitch immunity |
| 06/18/2002 | US6407961 Dual access memory array |
| 06/18/2002 | US6407958 Semiconductor integrated circuit device with split hierarchical power supply structure |
| 06/18/2002 | US6407942 Semiconductor memory device with a hierarchical word line configuration capable of preventing leakage current in a sub-word line driver |
| 06/13/2002 | WO2002046929A1 Method of controlling flash memory |
| 06/13/2002 | US20020071329 DRAM core refresh with reduced spike current |
| 06/13/2002 | US20020071315 Nonvolatile memory having embedded word lines |
| 06/13/2002 | US20020071310 Block architecture option circuit for nonvalatile semiconductor memory devices |
| 06/13/2002 | US20020071305 Register file scheme |
| 06/13/2002 | DE10062570C1 Read and write control circuit for magnetoresistive random-access memory has read/write amplifier pairs at opposite ends of bit lines |
| 06/12/2002 | CN1353460A Data storage possessing sereral storage unit |
| 06/11/2002 | US6405296 Asynchronous request/synchronous data dynamic random access memory |
| 06/11/2002 | US6405293 Selectively accessible memory banks for operating in alternately reading or writing modes of operation |
| 06/11/2002 | US6404700 Low power high density asynchronous memory architecture |
| 06/11/2002 | US6404694 Semiconductor memory device with address comparing functions |
| 06/11/2002 | US6404692 Semiconductor memory |
| 06/11/2002 | US6404682 Wired address compare circuit and method |
| 06/11/2002 | US6404681 Method for erasing data from a non-volatile semiconductor memory device |
| 06/11/2002 | US6404670 Multiple ports memory-cell structure |
| 06/11/2002 | US6404264 Fuse latch having multiplexers with reduced sizes and lower power consumption |
| 06/06/2002 | WO2002045093A1 Semiconductor memory device and address conversion circuit |
| 06/06/2002 | US20020069282 Method and system for distributing updates |
| 06/06/2002 | US20020067654 Synchronous memory modules and memory systems with selectable clock termination |
| 06/06/2002 | US20020067648 Asynchronous SRAM compatible memory device using DRAM cell and method for driving the same |
| 06/06/2002 | US20020067646 Method and apparatus for generating memory addresses for testing memory devices |
| 06/06/2002 | US20020067644 Wordline driver for ensuring equal stress to wordlines in multi row address disturb test and method of driving the wordline driver |
| 06/06/2002 | US20020067640 Semiconductor memory architecture |
| 06/06/2002 | US20020067639 Row decoder of a NOR-type flash memory device |
| 06/06/2002 | DE10129263A1 Non-volatile ferroelectric memory has pulse width generating unit for varying width of reproduction pulse and outputting varied width to word line driver to identify defective cell |
| 06/05/2002 | EP1210666A1 Linear flash memory compatible with compactflash mechanical interface |
| 06/05/2002 | EP1029326A4 Programmable access protection in a flash memory device |
| 06/04/2002 | US6401180 Bank history table for improved pre-charge scheduling of random access memory banks |
| 06/04/2002 | US6401164 Sectored semiconductor memory device with configurable memory sector addresses |
| 06/04/2002 | US6400642 Memory architecture |
| 06/04/2002 | US6400640 Method for memory addressing |
| 06/04/2002 | US6400639 Wordline decoder system and method |
| 06/04/2002 | US6400638 Wordline driver for flash memory read mode |
| 06/04/2002 | US6400637 Semiconductor memory device |
| 06/04/2002 | US6400636 Address generator for a semiconductor memory |
| 06/04/2002 | US6400635 Memory circuitry for programmable logic integrated circuit devices |
| 06/04/2002 | US6400597 Semiconductor memory device |
| 05/30/2002 | WO2002043319A2 Communications architecture for storage-based devices |
| 05/30/2002 | WO2002043072A2 Very small swing and low voltage cmos static memory |
| 05/30/2002 | WO2002005281A3 A high speed dram architecture with uniform access latency |
| 05/30/2002 | WO2002003459A3 High-speed low-power semiconductor memory architecture |
| 05/30/2002 | WO2001093271A3 MULTI-GENERATOR, PARTIAL ARRAY Vt, TRACKING SYSTEM TO IMPROVE ARRAY RETENTION TIME |
| 05/30/2002 | WO2001075898A3 Interface command architecture for synchronous flash memory |
| 05/30/2002 | WO2001075897A3 Synchronous flash memory |
| 05/30/2002 | US20020066058 Synchronous semiconductor device, and inspection system and method for the same |
| 05/30/2002 | US20020065997 Multi-port memory device and system for addressing the multi-port memory device |
| 05/30/2002 | US20020064083 Clock generating circuits controlling activation of a delay locked loop circuit on transition to a standby mode of a semiconductor memory device and methods for operating the same |
| 05/30/2002 | US20020064082 Semiconductor integrated circuit having circuit for correcting data output timing |
| 05/30/2002 | US20020064080 Semiconductor memory device |
| 05/29/2002 | DE10133595A1 Pufferschaltung, Speicherzugriffsverfahren, Speicherbauelement und Reed-Solomon-Decoder Buffer circuit, memory access method, memory device and Reed-Solomon decoder |
| 05/29/2002 | DE10121708A1 Halbleiterspeichereinrichtung und Verfahren zum Ändern von Ausgangsdaten dieser Einrichtung Semiconductor memory device and method of changing output data of this institution |
| 05/29/2002 | DE10057489A1 Integrated memory has memory cell field and control circuit connected to deactivation switch with delay stage activated by selection signal for delaying switching process |
| 05/29/2002 | DE10056881A1 Integrated memory has delay circuit for connection to control line to output signal delayed with respect to cell selection signal with capacitance for charging or discharging by current source |
| 05/29/2002 | DE10053425A1 Integrierter Speicher mit Zeilenzugriffsteuerung zur Aktivierung und Deaktivierung von Zeilenleitungen Built-in memory with row access control for activation and deactivation of row lines |
| 05/29/2002 | CN1351377A Voltage reverting circuits |
| 05/28/2002 | US6396764 Segmented memory architecture and systems and methods using the same |
| 05/28/2002 | US6396763 DRAM having a reduced chip size |
| 05/28/2002 | US6396755 Integrated memory with row access control to activate and precharge row lines, and method of operating such a memory |
| 05/28/2002 | US6396749 Dual-ported CAMs for a simultaneous operation flash memory |
| 05/28/2002 | US6396088 System with meshed power and signal buses on cell array |
| 05/23/2002 | WO2001075890A3 Synchronous flash memory with non-volatile mode register |
| 05/23/2002 | US20020062473 Semiconductor device and semiconductor storage device testing method |
| 05/23/2002 | US20020060945 Synchronous semiconductor device and method for latching input signals |
| 05/23/2002 | US20020060943 Semiconductor device having early operation high voltage generator and high voltage supplying method therefore |
| 05/23/2002 | US20020060938 Semiconductor memory device and data read method thereof |
| 05/23/2002 | US20020060937 Integrated memory having a voltage regulating circuit |
| 05/23/2002 | US20020060923 Addressing of memory matrix |
| 05/23/2002 | DE10055920A1 Integrated memory device transfers trim signals for voltage regulator circuit via address lines connected to line decoder |
| 05/22/2002 | EP0728359B1 Flash eprom integrated circuit architecture |