Patents
Sitemap › G11 - Information storage › G11C - Static stores › G11C 8 - Arrangements for selecting an address in a digital store
Patents for G11C 8 - Arrangements for selecting an address in a digital store (19,368)
12/2001
12/06/2001US20010048628 Method of controlling line memory
12/06/2001US20010048627 VPX bank architecture
12/06/2001US20010048616 Semiconductor device including multi-chip
12/06/2001US20010048613 Dual-ported cams for a simultaneous operation flash memory
12/06/2001US20010048610 Semiconductor memory device
12/06/2001US20010048121 Semiconductor memory device with block alignment function
12/05/2001EP1160793A2 Memory decoder and method of operation
12/05/2001CN1325547A Semiconductor circuit
12/05/2001CN1325533A Redundant form address decoder for memory system
12/04/2001US6327216 Full page increment/decrement burst for DDR SDRAM/SGRAM
12/04/2001US6327214 Multi-bank memory device having input and output amplifier shared by adjacent memory banks
12/04/2001US6327213 Semiconductor integrated circuit device having a hierarchical power source configuration
12/04/2001US6327207 Synchronizing data operations across a synchronization boundary between different clock domains using two-hot encoding
12/04/2001US6327195 Boosted-voltage drive circuit operable with high reliability and semiconductor memory device employing the same
12/04/2001US6327192 Method and circuit for providing a memory device having hidden row access and row precharge times
12/04/2001US6327191 Address signal generator in a semiconductor memory
12/04/2001US6327188 Synchronous random access memory
12/04/2001US6326813 Method and apparatus for high-speed edge-programmable timing signal generation
11/2001
11/29/2001WO2001091296A2 Block ram having multiple configurable write modes for use in a field programmable gate array
11/29/2001WO2001091128A2 Semiconductor memory and controlling method thereof
11/29/2001US20010046177 Semiconductor memory device
11/29/2001US20010046172 Integrated memory with row access control to activate and precharge row lines, and method of operating such a memory
11/29/2001US20010046171 VPX bank architecture
11/29/2001US20010046167 Semiconductor device including multi-chip
11/29/2001US20010046162 Dynamic memory word line driver scheme
11/29/2001US20010046161 Word line boost circuit
11/29/2001US20010046155 Circuits and methods for a memory cell with a trench plate trench capacitor and a vertical bipolar read device
11/29/2001US20010046154 Circuits and methods for a memory cell wirh a trench plate trench capacitor and a vertical bipolar read device
11/29/2001US20010046153 Semiconductor integrated circuit
11/29/2001US20010045581 Semiconductor device
11/29/2001DE10124112A1 Semiconducting memory for high speed operation has word drive circuit driving word line in response to word reset signal, main word signal and word decoder signal
11/29/2001CA2409214A1 Block ram having multiple configurable write modes for use in a field programmable gate array
11/28/2001EP1158536A2 Semiconductor memory device
11/28/2001EP1158535A2 Nonvolatile semiconductor memory device having electrically and collectively erasable characteristics
11/28/2001EP1158534A2 Semiconductor memory device
11/28/2001EP1158532A2 Semiconductor memory device
11/28/2001EP1158531A2 Semiconductor memory device
11/28/2001EP1158530A2 Nonvolatile semiconductor memory device having electrically and collectively erasable characteristics
11/28/2001EP1158527A2 Integrated memory with word line access control for activating and precharging word lines and driving method of such memory
11/28/2001EP1158526A2 Nonvolatile semiconductor memory device having electrically and collectively erasable characteristics
11/28/2001EP1158523A1 Address generator for generating addresses for an on chip trimming circuit
11/28/2001EP1157387A1 Full page increment/decrement burst for ddr sdram/sgram
11/28/2001EP0929901B1 Memory array, memory cell, and sense amplifier test and characterization
11/28/2001EP0929900B1 Data retention test for static memory cell
11/28/2001EP0929898B1 Memory block select using multiple word lines to address a single memory cell row
11/28/2001EP0929896B1 Memory including resistor bit-line loads
11/28/2001EP0929895B1 Active power supply filter
11/28/2001EP0806045B1 Decoded wordline driver with positive and negative voltage modes
11/27/2001US6324238 Bit counter stage, particularly for memories
11/27/2001US6324120 Memory device having a variable data output length
11/27/2001US6324117 Method of selecting a memory access line and an access line decoder for performing the same
11/27/2001US6324115 Semiconductor memory device with burst mode access
11/27/2001US6324096 Interface circuit and method for writing data into a non-volatile memory, and scan register
11/22/2001US20010043507 Synchronous semiconductor memory device capable of high speed reading and writing
11/22/2001US20010043506 Random access memory having independent read port and write port and process for writing to and reading from the same
11/22/2001US20010043502 Semiconductor memory device capable of efficient memory cell select operation with reduced element count
11/22/2001US20010043501 Redundancy circuitry for repairing defects in packaged memory having registers
11/22/2001US20010043494 Memory device with booting circuit capable of pre-booting before wordline selection
11/22/2001US20010043487 Semiconductor memory device
11/22/2001US20010043104 Delay circuit applied to semiconductor memory device having auto power-down function
11/22/2001DE10123514A1 Semiconductor memory component, such as multiport SRAM cell with two word lines and CMOS structure
11/22/2001DE10113198A1 Adressdecoder und Verfahren für einen beschleunigten Belastungstest desselben The same address decoder and method for an accelerated stress test
11/22/2001DE10022767A1 Address generator for generating addresses for on-chip trimming circuit, has memory latch stages for operation as counter synchronized to control signal or clock signal or as shift register
11/21/2001EP0929897B1 Dram
11/20/2001US6320819 Semiconductor device reconciling different timing signals
11/20/2001US6320817 Tri-stating address input circuit
11/20/2001US6320816 Column select latch for SDRAM
11/20/2001US6320814 Semiconductor device
11/20/2001US6320813 Decoding of a register file
11/20/2001US6320811 Multiport memory scheme
11/20/2001US6320800 Semiconductor memory and nonvolatile semiconductor memory having redundant circuitry for replacing defective memory cell
11/20/2001US6320792 Row decoding circuit for a semiconductor non-volatile electrically programmable memory and corresponding method
11/15/2001US20010042182 Asynchronous request/synchronous data dynamic random access memory
11/15/2001US20010040834 Semiconductor integrated circuit device having a hierarchical power source configuration
11/15/2001US20010040828 Multidimensional addressing architecture for electronic devices
11/15/2001US20010040827 Semiconductor memory device
11/15/2001US20010040822 Nonvolatile semiconductor memory
11/14/2001EP1154435A2 Write circuitry for a synchronous ram
11/14/2001EP1154375A1 Circuit for detection of external influences on a semiconductor chip
11/14/2001EP1153393A1 Improved word line boost circuit
11/13/2001US6317812 Device and method for controlling solid-state memory system
11/13/2001US6317382 Semiconductor memory device
11/13/2001US6317381 Method and system for adaptively adjusting control signal timing in a memory device
11/13/2001US6317379 Determine output of a read/write port
11/13/2001US6317367 FPGA with on-chip multiport memory
11/13/2001US6317366 Dynamic random access memory
11/13/2001US6317358 Efficient dual port DRAM cell using SOI technology
11/13/2001US6317352 Apparatus for implementing a buffered daisy chain connection between a memory controller and memory modules
11/08/2001WO2001084318A1 Methods and apparatus for authenticating data stored in memory
11/08/2001US20010039602 Semiconductor memory device and method of controlling the same
11/08/2001US20010038569 Semiconductor integrated circuit device
11/08/2001US20010038567 Semiconductor memory device for fast access
11/08/2001US20010038566 Memory component with short access time
11/08/2001US20010038558 String programmable nonvolatile memory with NOR architecture
11/08/2001US20010038551 Circuits and methods for a memory cell with a trench plate trench capacitor and a vertical bipolar read device.
11/08/2001US20010038104 Multilayer matrix-addressable logic device with a plurality of individually matrix-addressable and stacked thin films of an active material
11/07/2001EP0729613B1 Microcontroller conditionally skips updating latch for msb and directly drives lsb of memory address
11/07/2001EP0600151B1 Nonvolatile semiconductor memory device having electrically and collectively erasable characteristics
11/06/2001US6314051 Memory device having write latency
11/06/2001US6314049 Elimination of precharge operation in synchronous flash memory
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