| Patents for G11C 8 - Arrangements for selecting an address in a digital store (19,368) |
|---|
| 05/22/2001 | US6236618 Centrally decoded divided wordline (DWL) memory architecture |
| 05/22/2001 | US6236617 High performance CMOS word-line driver |
| 05/22/2001 | US6236615 Semiconductor memory device having memory cell blocks different in data storage capacity without influence on peripheral circuits |
| 05/22/2001 | US6236613 Semiconductor integrated circuit device having a hierarchical power source configuration |
| 05/22/2001 | US6236581 High voltage boosted word line supply charge pump and regulator for DRAM |
| 05/17/2001 | US20010001263 VPX bank architecture |
| 05/17/2001 | US20010001262 Semiconductor device |
| 05/17/2001 | US20010001206 Set of two memories on the same monolithic integrated circuit |
| 05/15/2001 | US6233707 Method and apparatus that allows the logic state of a logic gate to be tested when stopping or starting the logic gate's clock |
| 05/15/2001 | US6233694 Synchronization device for synchronous dynamic random-access memory |
| 05/15/2001 | US6233669 Memory address generator capable of row-major and column-major sweeps |
| 05/15/2001 | US6233199 Full page increment/decrement burst for DDR SDRAM/SGRAM |
| 05/15/2001 | US6233197 Multi-port semiconductor memory and compiler having capacitance compensation |
| 05/15/2001 | US6233196 Multi-bank integrated circuit memory devices with diagonal pairs of sub-banks |
| 05/15/2001 | US6233195 Multi-bank DRAM suitable for integration with processor on common semiconductor chip |
| 05/15/2001 | US6233191 Field programmable memory array |
| 05/15/2001 | US6233180 Device for determining the validity of word line conditions and for delaying data sensing operation |
| 05/10/2001 | WO2001033571A1 Flash memory wordline tracking across whole chip |
| 05/10/2001 | US20010000994 Semiconductor device reconciling different timing signals |
| 05/10/2001 | US20010000990 Semiconductor memory device |
| 05/10/2001 | US20010000989 Boosted-voltage drive circuit operable with high reliability and semiconductor memory device employing the same |
| 05/10/2001 | DE19952258A1 Integrated memory with folded bit line structure |
| 05/10/2001 | DE10031806A1 Flash-Speicherschaltung Flash memory circuit |
| 05/10/2001 | DE10020416A1 High-level generation circuit for semiconductor memory device, has detectors to output signals with high level, when feedback signal below threshold value is input |
| 05/08/2001 | US6230233 Wear leveling techniques for flash EEPROM systems |
| 05/08/2001 | US6229759 Semiconductor memory burst length count determination method |
| 05/08/2001 | US6229755 Wordline driving apparatus in semiconductor memory devices |
| 05/08/2001 | US6229754 Write through function for a memory |
| 05/08/2001 | US6229752 Semiconductor integrated circuit device |
| 05/08/2001 | US6229748 Memory device using one common bus line between address buffer and row predecoder |
| 05/08/2001 | US6229740 Voltage generation circuit having boost function and capable of preventing output voltage from exceeding prescribed value, and semiconductor memory device provided therewith |
| 05/08/2001 | US6229735 Burst read mode word line boosting |
| 05/08/2001 | US6229727 Method and apparatus for support of multiple memory devices in a single memory socket architecture |
| 05/08/2001 | US6229364 Frequency range trimming for a delay line |
| 05/03/2001 | US20010000817 Frame memory circuit |
| 05/03/2001 | US20010000816 Volatile lock architecture for individual block locking on flash memory |
| 05/03/2001 | US20010000815 Set of two memories on the same monolithic integrated circuit |
| 05/03/2001 | US20010000693 Synchronous semiconductor memory device capable of selecting column at high speed |
| 05/03/2001 | US20010000692 VPX bank architecture |
| 05/02/2001 | CN1293434A Buff circuit |
| 05/02/2001 | CN1293405A Embedded type MRAM containing dual read port |
| 05/02/2001 | CN1293402A Address reeling connection function of addressable storage equipment |
| 05/01/2001 | US6226219 Semiconductor memory with a plurality of memory banks |
| 05/01/2001 | US6226218 Row decoder driver for semiconductor memory device |
| 05/01/2001 | US6226199 Non-volatile semiconductor memory |
| 05/01/2001 | US6225849 High speed, high precision, power supply and process independent boost level clamping technique |
| 05/01/2001 | US6225828 Decoder for saving power consumption in semiconductor device |
| 04/26/2001 | WO2001029839A1 Method and apparatus for improving cell life of sequential counters stored in non-volatile memory |
| 04/26/2001 | DE19950159A1 Program control method for computer memory space, involves using buffers for programmed transfer to memory |
| 04/26/2001 | CA2387938A1 Method and apparatus for improving cell life of sequential counters stored in non-volatile memory |
| 04/25/2001 | EP1094467A2 Processing equipment with embedded MRAMS including dual read ports |
| 04/25/2001 | EP1025565A4 High speed memory self-timing circuitry and methods for implementing the same |
| 04/25/2001 | CN1292753A Memory expansion circuit for ink jet print head identification circuit |
| 04/24/2001 | US6223199 Method and apparatus for an N-NARY HPG gate |
| 04/24/2001 | US6222793 Memory devices having a restore start address counter |
| 04/24/2001 | US6222790 Semiconductor memory device in which data are read and written asynchronously with application of address signal |
| 04/24/2001 | US6222789 Sub word line driving circuit |
| 04/24/2001 | US6222788 Vertical gate transistors in pass transistor logic decode circuits |
| 04/18/2001 | EP1093228A1 Delay interpolator circuit and semiconductor integrated circuit having same |
| 04/17/2001 | US6219789 Microprocessor with coprocessing capabilities for secure transactions and quick clearing capabilities |
| 04/17/2001 | US6219687 Method and apparatus for an N-nary Sum/HPG gate |
| 04/17/2001 | US6219686 Method and apparatus for an N-NARY sum/HPG adder/subtractor gate |
| 04/17/2001 | US6219299 Programmable memory decode circuits with transistors with vertical gates |
| 04/17/2001 | US6219298 High-speed address decoders and related address decoding methods |
| 04/17/2001 | US6219297 Dynamic random access memory that can be controlled by a controller for a less integrated dynamic random access memory |
| 04/17/2001 | US6219296 Multiport memory cell having a reduced number of write wordlines |
| 04/17/2001 | US6219294 Multiplexed noisy-quiet power busing for improved area efficiencies and pause performance in DRAM memories |
| 04/17/2001 | US6219284 Programmable logic device with multi-port memory |
| 04/17/2001 | US6217213 Temperature sensing systems and methods |
| 04/12/2001 | DE19945684A1 Arithmetic bit shifting operation of digital input value |
| 04/12/2001 | DE10049934A1 Integrated circuit component has memory cell fields, pipeline block with sampling amplifiers used in common by memory cell fields, to which they are coupled via input/output lines |
| 04/12/2001 | DE10048372A1 Address control circuit has selection clock signal, generator of address conversion data for converting test object addresses to memory addresses, conversion data memory, address converter |
| 04/12/2001 | DE10039612A1 Semiconductor device has address decoder detects accesses to overshoot i.e. non-used memory addresses using only part of the outputs of pre-decoders |
| 04/11/2001 | EP0850480B1 Fast word line decoder for memory devices |
| 04/10/2001 | US6216246 Methods to make DRAM fully compatible with SRAM using error correction code (ECC) mechanism |
| 04/10/2001 | US6216147 Method and apparatus for an N-nary magnitude comparator |
| 04/10/2001 | US6216146 Method and apparatus for an N-nary adder gate |
| 04/10/2001 | US6215840 Method and apparatus for sequential memory addressing |
| 04/10/2001 | US6215837 Pipe counter signal generator processing double data in semiconductor device |
| 04/10/2001 | US6215729 Programmable counter circuit for generating a sequential/interleave address sequence |
| 04/10/2001 | US6215723 Semiconductor memory device having sequentially disabling activated word lines |
| 04/10/2001 | US6215720 High speed operable semiconductor memory device with memory blocks arranged about the center |
| 04/10/2001 | US6215719 Memory device having line address counter for making next line active while current line is processed |
| 04/10/2001 | US6215715 Integrated circuit memories including fuses between a decoder and a memory array for disabling defective storage cells in the memory array |
| 04/10/2001 | US6215708 Charge pump for improving memory cell low VCC performance without increasing gate oxide thickness |
| 04/10/2001 | US6215699 Nonvolatile semiconductor storage device having main block and redundancy block formed on different wells |
| 04/10/2001 | US6215687 Semiconductor device and process for manufacturing the same |
| 04/05/2001 | DE10046413A1 Integrated semiconductor circuit e.g. static random access memory, outputs pulse signal in response to functional signal of input and clock signals without holding functional signal |
| 04/04/2001 | EP1089287A1 Memory access line selection method, access line decoder and memory comprising such a decoder |
| 04/04/2001 | CN1290014A Flash memory and control method |
| 04/03/2001 | US6212615 Semiconductor circuit having burst counter circuit which is reduced the circuits passing from the clock input terminal to output terminal |
| 04/03/2001 | US6212128 Address transition detector in semiconductor memories |
| 04/03/2001 | US6212127 Semiconductor device and timing control circuit |
| 04/03/2001 | US6212125 Asynchronous semiconductor memory device with a control circuit that controls the latch timing of an input signal |
| 04/03/2001 | US6212121 Semiconductor memory device with multiple sub-arrays of different sizes |
| 04/03/2001 | US6212109 Dynamic memory array having write data applied to selected bit line sense amplifiers before sensing to write associated selected memory cells |
| 04/03/2001 | US6212090 Semiconductor device including a repetitive pattern |
| 04/03/2001 | US6211456 Method and apparatus for routing 1 of 4 signals |
| 03/29/2001 | WO2001022424A1 Asynchronously addressable clocked memory device and method of operating same |
| 03/29/2001 | DE19944738A1 Segmented word line architecture |