Patents
Patents for G11C 8 - Arrangements for selecting an address in a digital store (19,368)
01/2002
01/16/2002EP0738418B1 A method of testing a memory address decoder
01/15/2002US6339809 Memory unit and buffer access control circuit for updating an address when consecutively accessing upper and lower buffers
01/15/2002US6339560 Semiconductor memory based on address transitions
01/15/2002US6339553 Clock generating circuit having additional delay line outside digital DLL loop and semiconductor memory device including the same
01/15/2002US6339552 Semiconductor device
01/15/2002US6339542 Static random access memory (RAM) systems and storage cell for same
01/15/2002US6339358 Semiconductor integrated circuit
01/15/2002US6339353 Input circuit of a memory having a lower current dissipation
01/10/2002WO2002003459A2 High-speed low-power semiconductor memory architecture
01/10/2002WO2002003391A2 Method and low-power circuits used to generate accurate boosted wordline voltage for flash memory core cells in read mode
01/10/2002US20020004893 Feedback system for accomodating different memory module loading
01/10/2002US20020004867 Memory device which receives an external reference voltage signal
01/10/2002US20020004865 Protocol for communication with dynamic memory
01/10/2002US20020004319 Terminating circuit module used in a computer system
01/10/2002US20020003747 Semiconductor memory device
01/10/2002US20020003746 Memory address driver circuit
01/10/2002US20020003744 Programmable low voltage decode circuits with ultra-thin tunnel oxides
01/10/2002US20020003743 Memory device
01/10/2002US20020003742 Line segmentation in programmable logic devices having redundancy circuitry
01/10/2002US20020003740 System for automatic generation of suitable voltage source on motherboard
01/10/2002US20020003729 Semiconductor storage device and method for evaluating the same
01/09/2002CN1077727C Design method for semiconductor integrated circuit and its semiconductor integrated circuit device
01/08/2002US6338104 System including single connector pin supporter having two separate plurality of connector pins with one set of pins contacting state designating portion of memory card indicating write prohibit state
01/08/2002US6337831 Word line driving circuit for semiconductor memory device
01/08/2002US6337829 Semiconductor memory device and method for repairing thereof
01/08/2002US6337817 Semiconductor device having redundancy circuit
01/08/2002US6337810 Semiconductor memory device and method for reading data
01/08/2002US6337809 Semiconductor memory device capable of improving data processing speed and efficiency of a data input and output pin and related method for controlling read and write
01/08/2002US6337582 Buffer circuit
01/07/2002CA2313949A1 A method and apparatus for synchronization of row and column acces s operations
01/03/2002US20020002696 Semiconductor memory device
01/03/2002US20020001253 Integrated circuit device which outputs data after a latency period transpires
01/03/2002US20020001252 Semiconductor memory device and method of operation having delay pulse generation
01/03/2002US20020001250 Semiconductor memory for logic-hybrid memory
01/03/2002US20020001249 Semiconductor memory device improving data read-out access
01/03/2002US20020001240 Semiconductor memory device for providing address access time and data access time at a high speed
01/03/2002US20020001217 Semiconductor memory device with a hierarchical word line configuration capable of preventing leakage current in a sub-word line driver
01/03/2002US20020001216 Semiconductor device and process for manufacturing the same
01/03/2002US20020001215 Semiconductor memory device
01/03/2002US20020000867 Fuse latch having multiplexers with reduced sizes and lower power consumption
01/03/2002US20020000865 Semiconductor integrated circuit device
01/03/2002US20020000856 Delay locked loop with reduced noise response
01/03/2002US20020000855 Delay locked loop incorporating a ring type delay and counting elements
01/03/2002US20020000822 Semiconductor device provided with boost circuit consuming less current
01/03/2002US20020000583 System with meshed power and signal buses on cell array
01/03/2002DE10126084A1 Halbleiterspeichervorrichtung A semiconductor memory device
01/02/2002EP1168344A2 Information data recording and reproducing apparatus and methods
01/01/2002US6335902 Semiconductor memory device provided with generating means for internal clock signal for special mode
01/01/2002US6335900 Method and apparatus for selectable wordline boosting in a memory device
01/01/2002US6335898 Semiconductor IC device having a memory and a logic circuit implemented with a single chip
01/01/2002US6335897 Semiconductor memory device including redundancy circuit adopting latch cell
01/01/2002US6335885 Semiconductor device having a delay circuit for adjusting the timing of control signals
01/01/2002US6335880 Nonvolatile semiconductor memory
12/2001
12/27/2001WO2001052265A3 Decoder circuit
12/27/2001US20010055236 Semiconductor memory that enables high speed operation
12/25/2001US6334166 Processor system using synchronous dynamic memory
12/25/2001US6333894 Semiconductor storage device
12/25/2001US6333892 Synchronous semiconductor memory device capable of selecting column at high speed
12/25/2001US6333891 Circuit and method for controlling a wordline and/or stabilizing a memory cell
12/25/2001US6333890 Memory device with a plurality of common data buses
12/25/2001US6333889 Logic-merged semiconductor memory having high internal data transfer rate
12/25/2001US6333874 Semiconductor memory device having normal and standby modes, semiconductor integrated circuit and mobile electronic unit
12/25/2001US6333873 Semiconductor memory device with an internal voltage generating circuit
12/25/2001US6333869 Semiconductor memory device with readily changeable memory capacity
12/25/2001US6333662 Latch type level shift circuit
12/25/2001US6333656 Flip-flops
12/20/2001WO2001097204A1 Active matrix array devices
12/20/2001US20010054127 Address generator for generating addresses for an on-chip trim circuit
12/20/2001US20010053106 Semiconductor memory device
12/20/2001US20010053094 Programmable read-only memory generating identical word-line voltages from different power-supply voltages
12/20/2001US20010053093 Wordline decoder for flash memory
12/20/2001US20010053088 Circuits and methods for a memory cell with a trench plate trench capacitor and a vertical bipolar read device
12/20/2001US20010052803 Select signal generating circuit having clamp circuit for clamping select signals upon power on
12/20/2001US20010052794 Semiconductor circuit device having active and standby states
12/20/2001US20010052784 Voltage detecting circuit for semiconductor memory device
12/20/2001US20010052610 Reduced topography DRAM cell fabricated using a modified logic process and method for operating same
12/18/2001US6331963 Semiconductor memory device and layout method thereof
12/18/2001US6330977 Electronic labeling systems and methods and electronic card systems and methods
12/18/2001CA2176675C Multi-port random access memory
12/13/2001US20010052049 Bank selector circuit for a simultaneous operation flash memory device with a flexible bank partition architecture
12/13/2001US20010050878 Semiconductor memory device and control method
12/13/2001US20010050877 Semiconductor memory
12/13/2001US20010050876 Semiconductor memory device with bank configuration
12/13/2001US20010050870 Semiconductor memory device
12/13/2001US20010050728 Active matrix array devices
12/13/2001DE10126589A1 Semiconductor memory device for providing an address access time and data access time with greater speed
12/13/2001DE10106775A1 Voltage detection circuit for semiconducting storage component produces voltage level detection signal from amplified difference between reference and comparison signals
12/13/2001DE10025569A1 Integrierter Speicher mit Zeilenzugriffssteuerung zur Aktivierung und Vorladung von Zeilenleitungen und Verfahren zum Betrieb eines solchen Speichers Integrated memory having row access controller to activate and precharge of row lines and method of operation of such a memory
12/12/2001EP1162747A2 Line segmentation in programmable logic devices having redundancy circuitry
12/12/2001EP0783755B1 Initializing a read pipeline of a non-volatile sequential memory device
12/12/2001EP0730278B1 Semiconductor memory device
12/11/2001US6330682 Semiconductor memory device achieving faster operation based on earlier timings of latch operations
12/11/2001US6330205 Virtual channel synchronous dynamic random access memory
12/06/2001WO2001093273A2 Semiconductor memory with programmable bitline multiplexers
12/06/2001WO2001093271A2 MULTI-GENERATOR, PARTIAL ARRAY Vt, TRACKING SYSTEM TO IMPROVE ARRAY RETENTION TIME
12/06/2001WO2001093034A2 Dual-ported cams for a simultaneous operation flash memory
12/06/2001US20010049767 Efficient management method of memory cell array
12/06/2001US20010048632 Semiconductor memory integrated circuit
12/06/2001US20010048630 Semiconductor apparatus
12/06/2001US20010048629 Semiconductor memory apparatus