| Patents for G11C 8 - Arrangements for selecting an address in a digital store (19,368) |
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| 08/06/2002 | US6430089 Semiconductor device |
| 08/06/2002 | US6430088 Embedded static random access memory for field programmable gate array |
| 08/06/2002 | US6430087 Trimming method and system for wordline booster to minimize process variation of boosted wordline voltage |
| 08/06/2002 | US6430083 Register file scheme |
| 08/06/2002 | US6429065 Circuits and methods for a memory cell with a trench plate trench capacitor and a vertical bipolar read device |
| 08/01/2002 | WO2002059899A2 Mram bit line word line architecture |
| 08/01/2002 | WO2002059897A1 Multiple ports memory-cell structure |
| 08/01/2002 | US20020101778 Integrated circuit for storage and retrieval of multiple digital bits per nonvolatile memory cell |
| 08/01/2002 | US20020101774 Semiconductor memory device with controllable operation timing of sense amplifier |
| 08/01/2002 | US20020101762 Nonvolatile semiconductor memory device |
| 08/01/2002 | US20020100920 Sram device |
| 08/01/2002 | DE10162582A1 Pseudozufallsadressgenerator für einen 0,75M-Cache-Speicher Pseudo-random address generator for a 0.75M cache |
| 07/31/2002 | EP1227503A2 Semiconductor storage device formed to optimize test technique and redundancy technology |
| 07/31/2002 | EP1226586A1 Flash memory wordline tracking across whole chip |
| 07/30/2002 | US6426916 Memory device having a variable data output length and a programmable register |
| 07/30/2002 | US6426914 Floating wordline using a dynamic row decoder and bitline VDD precharge |
| 07/30/2002 | US6426913 Semiconductor memory device and layout method thereof |
| 07/30/2002 | US6426889 Semiconductor integrated circuit |
| 07/30/2002 | US6426655 Row decoder with switched power supply |
| 07/30/2002 | US6426560 Semiconductor device and memory module |
| 07/25/2002 | US20020099903 Memory system, method and predecoding circuit operable in different modes for selectively accessing multiple blocks of memory cells for simultaneous writing or erasure |
| 07/25/2002 | US20020099896 Integrated circuit device having double data rate capability |
| 07/25/2002 | US20020097630 Semiconductor memory device with a hierarchical word line configuration capable of preventing leakage current in a sub-word line driver |
| 07/25/2002 | US20020097629 Semiconductor memory device comprising more than two internal banks of different sizes |
| 07/25/2002 | US20020097627 Control circuit for a variable-voltage regulator of a nonvolatile memory with hierarchical row decoding |
| 07/25/2002 | US20020097610 Semiconductor device |
| 07/25/2002 | US20020097609 Semiconductor storage apparatus |
| 07/25/2002 | US20020097597 MRAM bit line word line architecture |
| 07/25/2002 | US20020097079 Addressable diode isolated thin film array |
| 07/25/2002 | US20020097074 Synchronous semiconductor device for adjusting phase offset in a delay locked loop |
| 07/25/2002 | US20020096679 Display driver IC |
| 07/25/2002 | DE10101995A1 Electrical or electronic switching arrangement comprises a detector unit and a comparator unit connected to the detector unit to compare the starting voltage with a reference voltage |
| 07/24/2002 | EP1225590A2 Burst access memory system |
| 07/24/2002 | EP1084496A4 Method and apparatus for sequential memory addressing |
| 07/24/2002 | CN1360314A Multiport memory based on dynamic random access memory core |
| 07/23/2002 | US6425103 Programmable moving inversion sequencer for memory bist address generation |
| 07/23/2002 | US6424592 Semiconductor integrated circuit having circuit for correcting data output timing |
| 07/23/2002 | US6424590 Semiconductor device |
| 07/23/2002 | US6424589 Semiconductor memory device and method for accessing memory cell |
| 07/23/2002 | US6424553 Multidimensional addressing architecture for electronic devices |
| 07/23/2002 | US6424176 Logic circuits used for address decoding |
| 07/18/2002 | US20020095544 Semiconductor memory device having memory cell block activation control circuit and method for controlling activation of memory cell blocks thereof |
| 07/18/2002 | US20020094697 DRAM cell having a capacitor structure fabricated partially in a cavity and method for operating same |
| 07/18/2002 | US20020093873 Semiconductor memory device |
| 07/18/2002 | US20020093872 Semiconductor integrated circuit, method of controlling the same, and variable delay circuit |
| 07/18/2002 | US20020093871 Synchronous memory devices with synchronized latency control circuits and methods of operating same |
| 07/18/2002 | US20020093870 Semiconductor memory device |
| 07/18/2002 | US20020093869 Apparatus and method for operation of multi-bank semiconductor memory device with an up/down counter |
| 07/18/2002 | US20020093850 Interface for a memory, and method for variable configuration of a memory apparatus |
| 07/18/2002 | US20020093846 Nonvolatile ferroelectric memory device and method for detecting weak cell using the same |
| 07/18/2002 | US20020093497 Scanning circuit , and imaging apparatus having the same |
| 07/18/2002 | US20020093370 Delay circuit using current source |
| 07/18/2002 | DE10154648A1 Semiconductor memory e.g. DRAM has sub word line driver which charges sub word line to boosting voltage irrespective of activation order between main word line signal and sub word line selection signal |
| 07/17/2002 | EP1223584A2 Memory device and method for handling out of range addresses |
| 07/16/2002 | US6421284 Semiconductor device |
| 07/16/2002 | US6421274 Semiconductor memory device and reading and writing method thereof |
| 07/11/2002 | US20020091890 Synchronous memory device having automatic precharge |
| 07/11/2002 | US20020089882 Simple method of allowing random access to rambus direct dram for short burst of data |
| 07/11/2002 | US20020089881 High speed semiconductor memory device with short word line switching time |
| 07/11/2002 | US20020089476 TFT LCD driver capable of reducing current consumption |
| 07/11/2002 | DE10136163A1 Konfiguration zur Erzeugung eines Taktes mit einer Verzögerungsschaltung und ein Verfahren hierfür Configuration for generating a clock having a delay circuit and a method thereof |
| 07/10/2002 | CN1357889A Synchronous memory module with optional clock terminal and memory system thereof |
| 07/10/2002 | CN1087472C Dynamical memory |
| 07/09/2002 | US6418078 Synchronous DRAM device having a control data buffer |
| 07/09/2002 | US6418077 Memory access methods and devices for use with random access memories |
| 07/09/2002 | US6418076 Semiconductor memory device utilizing access to memory area located outside main memory area |
| 07/09/2002 | US6418070 Memory device tester and method for testing reduced power states |
| 07/09/2002 | US6418050 Circuits and methods for a memory cell with a trench plate trench capacitor and a vertical bipolar read device |
| 07/04/2002 | WO2002052570A1 Techniques to synchronously operate a synchronous memory |
| 07/04/2002 | WO2001075623A3 Zero-latency-zero bus turnaround synchronous flash memory |
| 07/04/2002 | US20020087826 Address counter and address counting method |
| 07/04/2002 | US20020087790 Memory integrated circuit device which samples data upon detection of a strobe signal |
| 07/04/2002 | US20020087777 Synchronous integrated circuit device |
| 07/04/2002 | US20020085444 Memory device and method for handling out of range addresses |
| 07/04/2002 | US20020085443 Apparatus for selecting bank in semiconductor memory device |
| 07/04/2002 | US20020085429 Semiconductor memory device capable of outputting a wordline voltage via an external pin |
| 07/04/2002 | US20020085427 Semiconductor memory device for variably controlling drivability |
| 07/04/2002 | US20020085418 Nonvolatile memory system |
| 07/04/2002 | US20020085417 Burst access memory with zero wait states |
| 07/04/2002 | US20020084857 Delay locked loop for improving high frequency characteristics and yield |
| 07/04/2002 | DE10064649A1 Schnittstelle für einen Speicher und Verfahren zum variablen Konfigurieren einer Speichervorrichtung Interface for a memory and method for configuring a variable memory device |
| 07/03/2002 | EP1220226A2 Multi-port memory based on DRAM core |
| 07/02/2002 | US6415370 Semiconductor integrated circuit |
| 07/02/2002 | US6415366 Method and apparatus for load distribution across memory banks with constrained access |
| 07/02/2002 | US6415340 Method and apparatus for synchronous data transfers in a memory device with selectable data or address paths |
| 07/02/2002 | US6415339 Memory device having a plurality of programmable internal registers and a delay time register |
| 07/02/2002 | US6414901 Circuit for generating address of semiconductor memory device |
| 07/02/2002 | US6414900 Memory device and method for handling out of range addresses |
| 07/02/2002 | US6414898 Method to reduce peak current for RAS cycle sensing in DRAM using non-multiplexed row and column addresses to avoid damage to battery |
| 07/02/2002 | US6414892 Semiconductor memory device |
| 07/02/2002 | US6414883 Semiconductor memory device |
| 07/02/2002 | US6414876 Flash EEprom system |
| 07/02/2002 | US6414875 String programmable nonvolatile memory with NOR architecture |
| 07/02/2002 | US6414874 Nonvolatile semiconductor memory device having electrically and collectively erasable characteristics |
| 06/27/2002 | WO2001091128A3 Semiconductor memory and controlling method thereof |
| 06/27/2002 | US20020083286 Techniques to asynchronously operate a synchronous memory |
| 06/27/2002 | US20020080677 Semiconductor memory device |
| 06/27/2002 | US20020080661 Circuit configuration for controlling write and read operations in a magnetoresistive memory configuration |
| 06/27/2002 | US20020080651 Level shifter for converting a voltage level and a semiconductor memory device having the level shifter |
| 06/27/2002 | US20020080640 Dynamic RAM-and semiconductor device |