Patents
Sitemap › G11 - Information storage › G11C - Static stores › G11C 8 - Arrangements for selecting an address in a digital store
Patents for G11C 8 - Arrangements for selecting an address in a digital store (19,368)
11/2001
11/06/2001US6314048 Semiconductor memory device for fast access
11/06/2001US6314047 Low cost alternative to large dual port RAM
11/06/2001US6314044 Semiconductor integrated circuit device
11/06/2001US6314043 Erasing and parallel rewriting circuit for memory cell blocks, particularly for analog flash cells, and related operating method
11/06/2001US6314042 Fast accessible semiconductor memory device
11/06/2001US6314037 Semiconductor integrated circuit device using BiCMOS technology
11/06/2001US6314029 Memory device having I/O sense amplifier with variable current gain
11/01/2001WO2001082304A1 Semiconductor storage device
11/01/2001US20010036244 Accelerated carry generation
11/01/2001US20010036121 Internal regeneration of the address latch enable (ALE) signal of a protocol of management of a burst interleaved memory and related circuit
11/01/2001US20010036120 Fast accessing of a memory device
11/01/2001US20010036119 Voltage detection circuit, power-on/off reset circuit, and semiconductor device
11/01/2001US20010036111 Address decoder optimization
11/01/2001US20010036106 Nonvolatile semiconductor memory
11/01/2001US20010035786 Pre-charging circuit of an output buffer
10/2001
10/31/2001EP1150300A2 Semiconductor storage device, control device, and electronic apparatus
10/31/2001DE10109318A1 Halbleiterspeichervorrichtung für schnellen Zugriff A semiconductor memory device for fast access
10/31/2001DE10049349A1 Semiconductor memory (DRAM) device capable of reducing its power supply voltage, has for each word line a line decoder having n-channel transistor connected between gate of p-channel transistor and another n-channel transistor
10/31/2001CN1320242A Recording system, data recording device, memory device, and data recording method
10/30/2001US6310827 Electronic memory and electronic device provided with such a memory
10/30/2001US6310823 Circuit for generating internal column strobe signal in synchronous semiconductor memory device
10/30/2001US6310821 Clock-synchronous semiconductor memory device and access method thereof
10/30/2001US6310818 Semiconductor memory device and method of changing output data of the same
10/30/2001US6310816 Method and system for accessing rows in multiple memory banks within an integrated circuit
10/30/2001US6310815 Multi-bank semiconductor memory device suitable for integration with logic
10/30/2001US6310793 Segmented word line architecture for dividing up a word line into a plurality of banks for cell arrays having long bit lines
10/30/2001US6310506 Programmable setup/hold time delay network
10/25/2001US20010034819 Interleaved data path and output management architecture for an interleaved memory and load pulser circuit for outputting the read data
10/25/2001US20010034817 Read/write alignment scheme for port red uction of multi-port SRAM cells
10/25/2001US20010033524 Circuit for managing the transfer of data streams from a plurality of sources within a system
10/25/2001US20010033520 Device and method for repairing a memory array by storing each bit in multiple memory cells in the array
10/25/2001US20010033245 Interleaved memory device for burst type access in synchronous read mode with the two semi-arrays independently readable in random access asynchronous mode
10/24/2001EP1147519A1 Apparatus and method for optimizing die utilization and speed performance by register file splitting
10/24/2001EP1147518A1 Integrated electric and/or electronic system with means for insulating a functional module, corresponding device and method for insulation and use
10/24/2001EP0965130B1 Non-volatile memory enabling simultaneous reading and writing by time multiplexing a decode path
10/24/2001EP0829086B1 Technique for reconfiguring a high density memory
10/23/2001US6307806 Semiconductor integrated circuit and method of operating the same
10/23/2001US6307805 High performance semiconductor memory device with low power consumption
10/23/2001US6307804 Semiconductor memory device capable of efficient memory cell select operation with reduced element count
10/23/2001US6307796 Dynamic random access memory
10/23/2001US6307795 Semiconductor memory having multiple redundant columns with offset segmentation boundaries
10/23/2001US6307793 Memory device, coupling noise eliminator, and coupling noise elimination method
10/23/2001US6307779 Method and circuitry for bank tracking in write command sequence
10/23/2001US6307565 System for dual buffering of asynchronous input to dual port memory for a raster scanned display
10/18/2001US20010031027 Method and apparatus for high-speed edge-programmable timing signal generation
10/18/2001US20010030904 Memory device having a programmable register
10/18/2001US20010030903 Clock generating circuit ensuring a wide lock-allowing frequency range and allowing reduction in layout area as well as a semiconductor device provided with the same
10/18/2001US20010030902 Semiconductor memory for logic-hybrid memory
10/18/2001US20010030893 Memory architecture with single-port cell and dual-port (read and write) functionality
10/16/2001USRE37409 Memory and method for sensing sub-groups of memory elements
10/16/2001US6304937 Method of operation of a memory controller
10/16/2001US6304510 Memory device address decoding
10/16/2001US6304509 Semiconductor storage unit
10/16/2001US6304508 Semiconductor device
10/16/2001US6304498 Semiconductor memory device capable of suppressing degradation in operation speed after replacement with redundant memory cell
10/16/2001US6304485 Flash EEprom system
10/11/2001WO2001075898A2 Interface command architecture for synchronous flash memory
10/11/2001WO2001075897A2 Synchronous flash memory
10/11/2001WO2001075896A2 Flash with consistent latency for read operations
10/11/2001WO2001075895A2 Elimination of precharge operation in synchronous flash memory
10/11/2001WO2001075890A2 Synchronous flash memory with non-volatile mode register
10/11/2001WO2001075623A2 Zero-latency-zero bus turnaround synchronous flash memory
10/11/2001US20010029563 ATD generation in a synchronous memory
10/11/2001US20010028598 Column decoder circuit for page reading of a semiconductor memory
10/11/2001US20010028596 Semiconductor memory device
10/11/2001US20010028595 Semiconductor memory device having a word line activation block
10/11/2001US20010028591 Semiconductor memory device having normal and standby modes, semiconductor integrated circuit and mobile electronic unit
10/11/2001US20010028575 Static random access memory (RAM) systems and storage cell for same
10/11/2001US20010028114 Semiconductor device including memory unit and semiconductor module including memory units
10/11/2001US20010028090 Semiconductor circuit configuration
10/10/2001EP1143452A2 Memory circuitry for programmable logic integrated circuit devices
10/10/2001EP1141951A2 A digital memory structure and device, and methods for the management thereof
10/09/2001US6301649 Semiconductor circuit with address translation circuit that enables quick serial access in row or column directions
10/09/2001US6301189 Apparatus for generating write control signals applicable to double data rate SDRAM
10/09/2001US6301187 Synchronous type semiconductor memory device permitting reduction in ratio of area occupied by control circuit in chip area
10/09/2001US6301186 RAM cell with column clear
10/09/2001US6301146 Static random access memory (RAM) systems and storage cell for same
10/04/2001US20010027508 CD-ROM decoder
10/04/2001US20010026498 Memory configuration having a circuit for determining the activated memory array
10/04/2001US20010026497 Method and system for accessing rows in multiple memory banks within an integrated circuit
10/04/2001US20010026478 Semiconductor memory device
10/04/2001US20010026475 Semiconductor integrated circuit
10/04/2001US20010026474 Semiconductor storage device
10/04/2001US20010026472 Flash EEprom system
10/04/2001US20010026183 Signal processing circuits having a pair of delay locked loop (DLL) circuits for adjusting a duty-cycle of a periodic digital signal and methods of operating same
10/04/2001US20010026176 Decoding apparatus
10/04/2001EP1139569A1 Adjustment of the duty-cycle of a periodic digital signal with leading and triling edge DLLs
10/02/2001US6298429 Memory address generator capable of row-major and column-major sweeps
10/02/2001US6298007 Method and apparatus for eliminating false data in a page mode memory device
10/02/2001US6298005 Configurable memory block
10/02/2001US6298003 Boost circuit of DRAM with variable loading
10/02/2001US6297668 Serial device compaction for improving integrated circuit layouts
09/2001
09/27/2001WO2001071722A1 Multidimensional addressing architecture for electronic devices
09/27/2001US20010024399 Method for memory addressing
09/27/2001US20010024398 Memory device with support for unaligned access
09/27/2001US20010024383 Semiconductor memory device
09/27/2001US20010024382 Semiconductor memory device
09/27/2001US20010024135 Method and apparatus for generating a sequence of clock signals
09/27/2001US20010024131 Row selection circuit for fast memory devices
09/26/2001EP1137011A1 String programmable nonvolatile memory with NOR architecture
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