| Patents for G11C 8 - Arrangements for selecting an address in a digital store (19,368) |
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| 02/26/2002 | US6351432 Synchronous semiconductor memory apparatus and input information latch control method thereof |
| 02/26/2002 | US6351430 Semiconductor memory device having stable wordline operations |
| 02/26/2002 | US6351429 Binary to binary-encoded-ternary (BET) decoder using reordered logic |
| 02/26/2002 | US6351428 Programmable low voltage decode circuits with ultra-thin tunnel oxides |
| 02/26/2002 | US6351427 Stored write scheme for high speed/wide bandwidth memory devices |
| 02/26/2002 | US6351420 Voltage boost level clamping circuit for a flash memory |
| 02/26/2002 | US6351413 Nonvolatile memory device, in particular a flash-EEPROM |
| 02/26/2002 | US6351176 Pulsing of body voltage for improved MOS integrated circuit performance |
| 02/21/2002 | WO2002015193A2 Burst read word line boosting |
| 02/21/2002 | US20020023200 Method and apparatus for synchronous data transfers in a memory device with selectable data or address paths |
| 02/21/2002 | US20020023193 Semiconductor memory and address controlling method thereof |
| 02/21/2002 | US20020021617 Clock-synchronous semiconductor memory device |
| 02/21/2002 | US20020021615 Semiconductor integrated circuit |
| 02/21/2002 | US20020021598 Nonvolatile memory, system having nonvolatile memories, and data read method of the system |
| 02/21/2002 | US20020021595 Boot block flash memory control circuit; IC memory card and semiconductor memory device incorporating the same; and erasure method for boot block flash memory |
| 02/21/2002 | US20020021584 Circuit structure for providing a hierarchical decoding in semiconductor memory devices |
| 02/21/2002 | US20020021159 Delay circuit and method |
| 02/21/2002 | US20020021152 DLL circuit and method of generating timing signals |
| 02/19/2002 | US6349376 Method for decoding addresses using comparison with range previously decoded |
| 02/19/2002 | US6349072 Random access memory device |
| 02/19/2002 | US6349069 Semiconductor memory device |
| 02/14/2002 | WO2002013384A1 Timer circuit and semiconductor memory incorporating the timer circuit |
| 02/14/2002 | US20020019919 Control chipset having dual-definition pins for reducing circuit layout of memory slot |
| 02/14/2002 | US20020019918 Method and apparatus for synchronous data transfers in a memory device with selectable data or address paths |
| 02/14/2002 | US20020018539 Multi-bit counter |
| 02/14/2002 | US20020018513 Memory |
| 02/14/2002 | US20020018394 Semiconductor memory device |
| 02/14/2002 | US20020018393 Semiconductor memory device and memory system for improving bus efficiency |
| 02/14/2002 | US20020018392 Vpx bank architecture |
| 02/14/2002 | US20020018384 Semiconductor storage device, control device, and electronic apparatus |
| 02/14/2002 | US20020018375 Memory system |
| 02/14/2002 | US20020018360 Integrated memory having memory cells with a magnetoresistive storage effect |
| 02/14/2002 | US20020017923 Semiconductor integrated circuit and semiconductor logic circuit used in the integrated circuit |
| 02/14/2002 | DE10131651A1 Verzögerungsregelschleife zur Verwendung in einem Halbleiterspeicherbauteil Delay-locked loop for use in a semiconductor memory device |
| 02/14/2002 | DE10125724A1 Memory device, memory system and method for access to data in memory, for use in dynamic random-access memory units, in information technology |
| 02/14/2002 | DE10054521A1 Method for reading data from a memory arrangement e.g. for semiconductor memory devices such as MRAM, has address decoder connected to word- and to bit-line decoders |
| 02/13/2002 | CN1335995A A data writing/reading method, a de-interleaving method, a data processing method, a memory and a memory drive apparatus |
| 02/13/2002 | CN1335625A Storage cell with magnetic resistance storage effect for integrated memory |
| 02/12/2002 | US6347062 Semiconductor memory device |
| 02/12/2002 | US6347055 Line buffer type semiconductor memory device capable of direct prefetch and restore operations |
| 02/12/2002 | US6347052 Word line decoding architecture in a flash memory |
| 02/07/2002 | US20020016895 Method and apparatus for synchronous data transfers in a memory device with selectable data or address paths |
| 02/07/2002 | US20020016885 Method and apparatus for synchronous data transfers in a memory device with selectable data or address paths |
| 02/07/2002 | US20020016884 Method and apparatus for synchronous data transfers in a memory device with selectable data or address paths |
| 02/07/2002 | US20020016876 System having double data transfer rate and integrated circuit therefor |
| 02/07/2002 | US20020016032 Semiconductor device, method for refreshing the same, and electronic equipment |
| 02/07/2002 | US20020015353 Programmable counter circuit for generating a sequential/interleave address sequence |
| 02/07/2002 | US20020015351 Method of operating a memory device having a variable data input length |
| 02/07/2002 | US20020015350 Fast accessible semiconductor memory device |
| 02/07/2002 | US20020015339 Data storage device and data storing method |
| 02/07/2002 | US20020015338 Delay locked loop for use in semiconductor memory device |
| 02/07/2002 | US20020015333 Semiconductor memory device |
| 02/07/2002 | US20020015328 Semiconductor integrated circuit |
| 02/06/2002 | EP1177558A1 Ampic dram |
| 02/05/2002 | US6345013 Latched row or column select enable driver |
| 02/05/2002 | US6345012 Tri-stating address input circuit |
| 02/05/2002 | US6344764 Semiconductor integrated circuit device |
| 02/05/2002 | US6343740 Oblique access to image data for reading apparatus |
| 01/31/2002 | WO2002009119A1 Inner voltage level control circuit, semiconductor storage, and method for controlling them |
| 01/31/2002 | WO2002009118A1 Semiconductor memory and control method |
| 01/31/2002 | US20020013879 Flash memory array access method and device |
| 01/31/2002 | US20020012284 Semiconductor memory device and method for accessing memory cell |
| 01/31/2002 | US20020012282 Semiconductor memory and nonvolatile semiconductor memory having redundant circuitry for replacing defective memory cell |
| 01/31/2002 | US20020012276 Semiconductor memory device having read data multiplexer |
| 01/31/2002 | US20020012262 High-speed low-power semiconductor memory architecture |
| 01/31/2002 | DE10133281A1 Memory device e.g. multiport SRAM used in integrated circuit, has switch connected between write data bit line and storage node, which conducts only when both write word line and write control line are active |
| 01/30/2002 | EP1176602A1 Flash EPROM integrated circuit architecture |
| 01/30/2002 | CN1333564A Memory |
| 01/30/2002 | CN1078721C Data protection circuit |
| 01/29/2002 | US6343355 Sequence controller capable of executing different kinds of processing at respective periods |
| 01/29/2002 | US6343348 Apparatus and method for optimizing die utilization and speed performance by register file splitting |
| 01/29/2002 | US6343045 Methods to reduce the effects of leakage current for dynamic circuit elements |
| 01/29/2002 | US6343044 Super low-power generator system for embedded applications |
| 01/29/2002 | US6343042 DRAM core refresh with reduced spike current |
| 01/29/2002 | US6342808 High voltage generating circuit |
| 01/29/2002 | US6342796 Delay locked loop having fast locking time |
| 01/24/2002 | US20020010828 Bank selector circuit for a simultaneous operation flash memory device with a flexible bank partition architecture |
| 01/24/2002 | US20020009834 Semiconductor IC device having a memory and a logic circuit implemented with a single chip |
| 01/24/2002 | US20020008564 Decoder element for generating an output signal having three different potentials and an operating method for the decoder element |
| 01/24/2002 | DE10033486A1 Integrated memory (MRAM), whose memory cells contain magnetoresistive memory effect |
| 01/24/2002 | DE10033441A1 Circuit generating correctioon signals is integrated, dynamic semiconductor memories (DRAM) |
| 01/23/2002 | EP0935802B1 Staggered row line firing in a single ras cycle |
| 01/23/2002 | CN1078378C Semiconductor memory device having plurality of rwo address strobe signals |
| 01/22/2002 | US6341098 Semiconductor integrated circuit device having hierarchical power source arrangement |
| 01/22/2002 | US6340825 Method of designing semiconductor integrated circuit device and semiconductor integrated circuit device |
| 01/17/2002 | WO2002005287A1 Addressing of memory matrix |
| 01/17/2002 | WO2002005285A2 Flash memory architecture implementing simultaneously programmable multiple flash memory banks that are host compatible |
| 01/17/2002 | WO2002005283A1 Method and apparatus for synchronization of row and column access operations |
| 01/17/2002 | WO2002005281A2 A high speed dram architecture with uniform access latency |
| 01/17/2002 | US20020006074 Elimination of precharge operation in synchronous flash memory |
| 01/17/2002 | US20020006073 Decoding circuit for controlling activation of wordlines in a semiconductor memory device |
| 01/17/2002 | US20020006072 Memory device |
| 01/17/2002 | CA2805048A1 A high speed dram achitecture with uniform access latency |
| 01/17/2002 | CA2803037A1 Method and apparatus for synchronization of row and column access operations |
| 01/17/2002 | CA2415218A1 Method and apparatus for synchronization of row and column access operations |
| 01/17/2002 | CA2414920A1 A high speed dram architecture with uniform access latency |
| 01/16/2002 | EP1172957A1 Memory circuit, and synchronous detection circuit |
| 01/16/2002 | EP1172821A1 Semiconductor storage device and method for evaluating the same |
| 01/16/2002 | EP1172820A1 Programmable and electrically erasable serial readout memory by anticipation |
| 01/16/2002 | EP0963587B1 High voltage nmos pass gate for flash memory with high voltage generator |