Patents
Patents for G11C 8 - Arrangements for selecting an address in a digital store (19,368)
03/2015
03/05/2015US20150063052 Independently addressable memory array address spaces
03/05/2015US20150063022 Apparatuses and methods involving accessing distributed sub-blocks of memory cells
03/05/2015US20150063000 Semiconductor device and control method of the same
03/03/2015US8972819 Memory circuit incorporating radiation-hardened memory scrub engine
03/03/2015US8971148 Word line selection circuit and row decoder
03/03/2015US8971147 Control gate word line driver circuit for multigate memory
03/03/2015US8971146 Dual-port SRAM with bit line clamping
03/03/2015US8971145 Synchronous multiple port memory with asynchronous ports
03/03/2015US8971143 Semiconductor device periodically updating delay locked loop circuit
03/03/2015US8971139 Semiconductor device and data processing system
03/03/2015US8971135 Semiconductor memory device receiving data in response to data strobe signal, memory system including the same and operating method thereof
03/03/2015US8971132 Semiconductor device, method for controlling the same, and semiconductor system
03/03/2015US8971107 Emulation of static random access memory (SRAM) by magnetic random access memory (MRAM)
02/2015
02/26/2015US20150055430 Nonvolatile memory device and related wordline driving method
02/26/2015US20150055394 Semiconductor Device
02/26/2015DE102007036989B4 Verfahren zum Betrieb einer Speichervorrichtung, Speichereinrichtung und Speichervorrichtung A method of operating a memory device, storage device and storage device
02/24/2015US8964499 Row decoding circuit
02/24/2015US8964488 Non-volatile memory device using variable resistance element with an improved write performance
02/24/2015US8964456 Semiconductor memory with similar RAM and ROM cells
02/24/2015US8964451 Memory cell system and method
02/19/2015US20150049571 Memory control device, control method of memory control device, information processing apparatus
02/19/2015US20150049570 Memory device, memory system including the same, operating method thereof
02/19/2015US20150049569 Memory device
02/19/2015US20150049568 Memory access control in a memory device
02/17/2015USRE45378 Method for receiving data
02/17/2015US8959291 Two-port memory capable of simultaneous read and write
02/17/2015US8958265 Nearest neighbor serial content addressable memory
02/17/2015US8958264 Semiconductor integrated circuit
02/17/2015US8958263 Semiconductor device
02/17/2015US8958262 Bank selection circuit and memory device having the same
02/17/2015US8958258 Semiconductor device and test method thereof
02/17/2015US8958246 Vertically foldable memory array structure
02/17/2015US8958244 Split block decoder for a nonvolatile memory device
02/17/2015US8958230 Nonvolatile semiconductor memory device
02/17/2015US8958229 Nonvolatile memory device and method of fabricating same
02/17/2015US8957763 RFID access method using an indirect memory pointer
02/12/2015US20150043297 Active control device and semiconductor device including the same
02/12/2015US20150043290 Memory module
02/11/2015CN104347105A Ram输出寄存处理方法 Ram output registers approach
02/10/2015USRE45366 Method of writing data to a memory
02/10/2015US8954821 Memory device having address and command selectable capabilities
02/10/2015US8953410 Semiconductor integrated circuit capable of controlling read command
02/10/2015US8953409 Semiconductor device capable of minimizing mutual effects between two different operations therein
02/10/2015US8953408 Semiconductor memory device and method of manufacturing the same
02/10/2015US8953407 Sub word line driver and semiconductor integrated circuit device
02/10/2015US8953406 Semiconductor module includes semiconductor chip initialized by reset signal
02/10/2015US8953403 Semiconductor memory device
02/10/2015US8953396 NAND interface
02/10/2015US8953391 Semiconductor apparatus
02/10/2015US8953381 Semiconductor memory device and method of operating the same
02/10/2015US8953372 Memory device readout using multiple sense times
02/10/2015US8953355 Memory dies, stacked memories, memory devices and methods
02/10/2015US8952721 Semiconductor device
02/05/2015WO2015016973A1 Dual port memory cell
02/04/2015EP2831879A1 Data selection and identification
02/04/2015CN102124525B 虚拟存储器接口 Virtual memory interface
02/03/2015US8949519 Simulating a memory circuit
02/03/2015US8949473 Hybrid memory blade
02/03/2015US8947972 Dynamic address grouping for parallel programming in non-volatile memory
02/03/2015US8947971 Semiconductor device generating a clock signal when required
02/03/2015US8947970 Word line driver circuits and methods for SRAM bit cell with reduced bit line pre-charge voltage
02/03/2015US8947969 Secondary memory units and systems including the same
02/03/2015US8947934 Sharing local control lines across multiple planes in a memory device
02/03/2015US8947929 Flash-based soft information generation
02/03/2015US8947903 Memory chip with more than one type of memory cell
02/03/2015US8947233 Methods and systems of a multiple radio frequency network node RFID tag
02/03/2015US8947070 Apparatus and method for testing driver writeability strength on an integrated circuit
01/2015
01/29/2015US20150029804 Apparatuses and methods for adjusting deactivation voltages
01/28/2015CN104318946A 具有芯片识别符结构的可垂直堆叠的裸片 Vertically stacked die structure having a chip identifier
01/27/2015US8942041 Memory device and column decoder for reducing capacitive coupling effect on adjacent memory cells
01/27/2015US8942040 Non-volatile semiconductor memory device capable of improving failure-relief efficiency
01/27/2015US8942030 Structure and method for SRAM cell circuit
01/27/2015US8942029 Memory device
01/27/2015CA2638421C Content data recording apparatus and method
01/22/2015US20150023121 Memory refresh methods, memory section control circuits, and apparatuses
01/21/2015CN104299638A 配置在存储库及扇区内且与解码器相关联的存储器阵列 Configuration memory array within the sector and is the repository and associated with the decoder
01/20/2015US8937846 Write level training using dual frequencies in a double data-rate memory device interface
01/20/2015US8937843 Semiconductor device having counter circuit
01/20/2015US8937842 Systems and methods for data strobe calibration for timing variations
01/20/2015US8937839 Data paths using a first signal to capture data and a second signal to output data and methods for providing data
01/20/2015US8937624 Method and apparatus for translating memory access address
01/15/2015WO2015006563A1 A monolithic three dimensional (3d) random access memory (ram) array architecture with bitcell and logic partitioning
01/15/2015WO2015005920A1 Storage device write pulse control
01/15/2015US20150016202 Memory devices, systems and methods employing command/address calibration
01/15/2015US20150016198 Multiple Power Domain Circuit and Related Method
01/13/2015US8934317 Semiconductor memory devices having internal clock signals and memory systems including such memory devices
01/13/2015US8934300 Memory array structure and operating method and manufacturing method for the same
01/13/2015US8934291 Interleaved array architecture
01/13/2015US8934287 Multiple-port SRAM device
01/13/2015US8934286 Complementary metal-oxide-semiconductor (CMOS) dynamic random access memory (DRAM) cell with sense amplifier
01/08/2015US20150009774 Semiconductor devices and semiconductor systems including the same
01/08/2015US20150009773 Volume select for affecting a state of a non-selected memory volume
01/08/2015US20150009751 Methods and systems to selectively boost an operating voltage of, and controls to an 8t bit-cell array and/or other logic blocks
01/08/2015DE102004050037B4 Speicherbauelement, Speichersystem und Betriebsmodussetzverfahren Memory device, memory system and operating mode setting procedure
01/07/2015CN104272389A 用于低功率多电平经编码信号的方法及设备 For low power multi-level encoded signal, the method and apparatus
01/06/2015US8929173 Data strobe control device
01/06/2015US8929171 Voltage supply controller, nonvolatile memory device and memory system
01/06/2015US8929170 Memory device, memory system, and power management method
01/06/2015US8929165 Memory device
01/06/2015US8929126 Array voltage regulating technique to enable data operations on large cross-point memory arrays with resistive memory elements
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