| Patents for G11C 8 - Arrangements for selecting an address in a digital store (19,368) |
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| 05/22/2002 | CN1350369A Storage device, method for accessing storage device and Read-solomon decoder |
| 05/21/2002 | US6393600 Skew-independent memory architecture |
| 05/21/2002 | US6393562 Method and apparatus for preventing fraudulent access in a conditional access system |
| 05/21/2002 | US6392958 Asynchronous SRAM compatible memory device using DRAM cell and method for driving the same |
| 05/21/2002 | US6392956 Semiconductor memory that enables high speed operation |
| 05/21/2002 | US6392952 Memory refresh circuit and memory refresh method |
| 05/21/2002 | US6392951 Semiconductor storage device |
| 05/21/2002 | US6392950 Semiconductor device including multi-chip |
| 05/21/2002 | US6392945 Semiconductor memory device |
| 05/21/2002 | US6392940 Semiconductor memory circuit |
| 05/21/2002 | US6392909 Semiconductor memory device having fixed CAS latency in normal operation and various CAS latencies in test mode |
| 05/16/2002 | US20020057618 Semiconductor integrated circuit device having hierarchical power source arrangement |
| 05/16/2002 | US20020057611 Semiconductor memory device |
| 05/16/2002 | US20020057607 Activation of word lines in semiconductor memory device |
| 05/16/2002 | US20020057595 Variable capacity semiconductor memory device |
| 05/16/2002 | US20020057589 Semiconductor device including a repetitive pattern |
| 05/16/2002 | US20020057129 Semiconductor integrated circuit |
| 05/16/2002 | DE10121649A1 Auswahlsignal-Erzeugungsschaltung mit einer Klemmschaltung zum Klemmen von Auswahlsignalen beim Einschalten Selection signal generating circuit with a clamp circuit for clamping of selection signals when switching |
| 05/15/2002 | EP1116239B1 Simultaneous operation flash memory device with a flexible bank partition architecture |
| 05/15/2002 | EP1116236B1 Method of making flexibly partitioned metal line segments for a simultaneous operation flash memory device with a flexible bank partition architecture |
| 05/14/2002 | US6389521 Data transfer control of a video memory having a multi-divisional random access memory and a multi-divisional serial access memory |
| 05/14/2002 | US6388944 Memory component with short access time |
| 05/14/2002 | US6388939 Dual port sram |
| 05/14/2002 | US6388908 Recording system, data recording device, memory device, and data recording method |
| 05/14/2002 | US6388472 Word line decoder |
| 05/09/2002 | US20020055016 Magneto-resistive element |
| 05/09/2002 | US20020054537 Internal addressing structure of a semiconductor memory |
| 05/09/2002 | US20020054535 Random access memory having a read/write address bus and process for writing to and reading from the same |
| 05/09/2002 | US20020054533 Semiconductor memory device having SRAM interface |
| 05/09/2002 | US20020054531 Non-volatile semiconductor memory device |
| 05/09/2002 | US20020054523 Activation of word lines in semiconductor memory device |
| 05/09/2002 | US20020054519 Semiconductor memory and controlling method thereof |
| 05/09/2002 | US20020054517 Sequence circuit and semiconductor device using sequence circuit |
| 05/09/2002 | US20020054516 Semiconductor device |
| 05/09/2002 | US20020054510 Non-volatile semiconductor memory device for selectively re-checking word lines |
| 05/09/2002 | US20020054045 Memory device and method |
| 05/09/2002 | US20020053924 Semiconductor integrated circuits with power reduction mechanism |
| 05/09/2002 | US20020053691 Reduced topography DRAM cell fabricated using a modified logic process and method for operating same |
| 05/08/2002 | EP1204119A2 Sequence circuit and semiconductor device using sequence circuit |
| 05/08/2002 | EP1204118A2 Semiconductor memory device having SRAM interface |
| 05/08/2002 | DE10051988A1 Voltage level converter circuit for controlling bit lines has blocking transistor located between inverter circuit transistor outputs |
| 05/07/2002 | US6385128 Random access memory having a read/write address bus and process for writing to and reading from the same |
| 05/07/2002 | US6385127 Synchronous semiconductor device and method for latching input signals |
| 05/07/2002 | US6385126 Clock synchronization circuit and semiconductor device having the same |
| 05/07/2002 | US6385123 Integrated circuit having a decoder unit and an additional input of a decoder unit to determine a number of outputs to be activated |
| 05/07/2002 | US6385122 Row and column accessible memory with a built-in multiplex |
| 05/07/2002 | US6385121 Semiconductor memory device having a plurality of banks sharing a column control unit |
| 05/07/2002 | US6385107 Architecture for handling internal voltages in a non-volatile memory, particularly in a single-voltage supply type of dual-work flash memory |
| 05/07/2002 | US6385100 Semiconductor memory device with improved column selecting operation |
| 05/07/2002 | US6385091 Read reference scheme for non-volatile memory |
| 05/07/2002 | US6385075 Parallel access of cross-point diode memory arrays |
| 05/07/2002 | US6384646 Select signal generating circuit having clamp circuit for clamping select signals upon power on |
| 05/07/2002 | US6384623 Semiconductor integrated circuits with power reduction mechanism |
| 05/02/2002 | WO2002035548A2 Storing device, storing control method and program |
| 05/02/2002 | WO2001093034A3 Dual-ported cams for a simultaneous operation flash memory |
| 05/02/2002 | US20020052071 Upscaled clock feeds memory to make parallel waves |
| 05/02/2002 | US20020051403 Sub word line drive circuit for semiconductor memory device |
| 05/02/2002 | US20020051402 Pattern layout of transfer transistors employed in row decoder |
| 05/02/2002 | US20020051397 Semiconductor device |
| 05/02/2002 | US20020051389 Activation of word lines in semiconductor memory device |
| 05/02/2002 | US20020051388 Memory device with pipelined address path |
| 05/02/2002 | US20020050959 High speed video frame buffer |
| 05/02/2002 | US20020050850 Voltage switching circuit |
| 05/02/2002 | US20020050448 Electronic driver circuit for word lines in a memory matrix, and memory apparatus |
| 05/02/2002 | EP1202282A2 Integrated memory with row line access control for asserting or de-asserting row conductors |
| 05/02/2002 | EP1202281A1 Semiconductor memory device internally provided with logic circuit which can be readily controlled and controlling method thereof |
| 05/02/2002 | DE10149387A1 Halbleiterspeicherbauelement mit Wortleitungs-Niederspannungszufuhrleitungen A semiconductor memory device having wordline low voltage supply lines |
| 05/02/2002 | DE10135065A1 Halbleiterspeichervorrichtung und Verfahren für den Zugriff auf eine Speicherzelle A semiconductor memory device and method for accessing a memory cell |
| 05/02/2002 | DE10130752A1 Halbleiterspeichervorrichtung und Steuerverfahren A semiconductor memory device and control method |
| 05/02/2002 | DE10050770A1 Circuit for controlling memory matrix word lines makes and maintains low impedance connection from detection of sensed potential changing towards second potential to defined extent |
| 05/01/2002 | CN1084051C Method of driving field effect transistor |
| 04/30/2002 | US6381708 Method for decoding addresses for a defective memory array |
| 04/30/2002 | US6381670 Flash memory array having maximum and minimum threshold voltage detection for eliminating over-erasure problem and enhancing write operation |
| 04/30/2002 | US6381195 Circuit, apparatus and method for generating address |
| 04/30/2002 | US6381192 Address buffer in a flash memory |
| 04/30/2002 | US6381191 Fast accessible dynamic type semiconductor memory device |
| 04/30/2002 | US6381186 Dynamic random access memory |
| 04/30/2002 | US6381182 Combined tracking of WLL and VPP low threshold voltage in DRAM array |
| 04/30/2002 | US6381174 Non-volatile memory device with redundant columns |
| 04/30/2002 | US6381168 Circuits and methods for a memory cell with a trench plate trench capacitor and a vertical bipolar read device |
| 04/30/2002 | US6380553 Multilayer matrix-addressable logic device with a plurality of individually matrix-addressable and stacked thin films of an active material |
| 04/25/2002 | US20020048210 Semiconductor memory device having hierarchical word line structure |
| 04/25/2002 | US20020048208 Semiconductor device, refreshing method thereof, memory system, and electronic instrument |
| 04/25/2002 | US20020048205 Dynamic random access memory |
| 04/25/2002 | US20020048201 First-in, first-out (FIFO) memory cell architecture |
| 04/25/2002 | US20020048197 Sdram having posted cas function of jedec standard |
| 04/25/2002 | US20020048191 Semiconductor device and testing method thereof |
| 04/25/2002 | DE10047251A1 1-aus-N-Decodierschaltung 1-of-N decoder circuit |
| 04/24/2002 | CN1346151A Semicondcutor IC |
| 04/24/2002 | CN1346129A Method for regulating threshold value of first-in first-out buffer |
| 04/23/2002 | US6378102 Synchronous semiconductor memory device with multi-bank configuration |
| 04/23/2002 | US6378032 Bank conflict avoidance in multi-bank DRAMS with shared sense amplifiers |
| 04/23/2002 | US6378020 System having double data transfer rate and intergrated circuit therefor |
| 04/23/2002 | US6377512 Clock synchronous type semiconductor memory device that can switch word configuration |
| 04/23/2002 | US6377509 Semiconductor integrated circuit |
| 04/23/2002 | US6377506 Semiconductor device |
| 04/23/2002 | US6377502 Semiconductor device that enables simultaneous read and write/erase operation |
| 04/23/2002 | US6377496 Word line voltage regulation circuit |
| 04/23/2002 | US6377492 Memory architecture for read and write at the same time using a conventional cell |
| 04/23/2002 | US6377487 Flash memory device |