Patents
Sitemap › G11 - Information storage › G11C - Static stores › G11C 8 - Arrangements for selecting an address in a digital store
Patents for G11C 8 - Arrangements for selecting an address in a digital store (19,368)
11/2000
11/16/2000DE19920992A1 Verfahren für einen Zugriff auf eine Speichereinrichtung A method for accessing a memory device
11/15/2000EP1052647A2 Semiconductor device
11/14/2000US6148388 Extended page mode with memory address translation using a linear shift register
11/14/2000US6148363 Device and method for controlling solid-state memory system
11/14/2000US6147927 Synchronous semiconductor memory device capable of more reliable communication of control signal and data
11/14/2000US6147923 Voltage boosting circuit
11/14/2000US6147915 Semiconductor integrated circuit
11/14/2000US6147914 On-chip word line voltage generation for DRAM embedded in logic process
11/14/2000US6147905 Non-volatile semiconductor memory device
11/14/2000US6147535 Clock phase generator for controlling operation of a DRAM array
11/09/2000WO2000067128A1 Linear flash memory compatible with compactflash® mechanical interface
11/08/2000EP1050885A1 A multiport storage array
11/08/2000EP1050884A1 A multiport memory system with write conflict detection
11/08/2000EP1050883A1 Circuits for controlling the storage of data into memory
11/08/2000EP1050822A2 Method for accessing a memory device
11/08/2000EP1050818A1 Computer memory access
11/08/2000CN1272673A Production of improved oblique pointer
11/07/2000USH1915 Hybrid static RAM circuit
11/07/2000US6145051 Moving sectors within a block of information in a flash memory mass storage architecture
11/07/2000US6145023 Information storage and information processing system utilizing state-designating member provided on supporting card surface which produces write-permitting or write-inhibiting signal
11/07/2000US6144617 Synchronous semiconductor storage device
11/07/2000US6144612 Address decoder for a synchronous type memory capable of preventing multi-wordline selection
11/07/2000US6144610 Distributed circuits to turn off word lines in a memory array
11/07/2000US6144609 Multiport memory cell having a reduced number of write wordlines
11/07/2000US6144608 Dual-port memory
11/07/2000US6144589 Boosting circuit, particularly for a memory device
11/07/2000US6144325 Register file array having a two-bit to four-bit encoder
10/2000
10/31/2000US6141291 Semiconductor memory device
10/31/2000US6141289 Structure of random access memory formed of multibit cells
10/31/2000US6141283 Method and apparatus for dynamically placing portions of a memory in a reduced power consumption state
10/31/2000US6141278 Semiconductor memory device allowing fast successive selection of word lines in a test mode operation
10/31/2000US6141269 Semiconductor integrated circuit device using BiCMOS technology
10/31/2000US6141267 Defect management engine for semiconductor memories and memory systems
10/31/2000US6141265 Clock synchronous memory
10/31/2000US6141262 Boosting circuit with boosted voltage limited
10/31/2000US6141249 Organization of blocks within a nonvolatile memory unit to effectively decrease sector write operation time
10/31/2000US6141236 Interleaved stitch using segmented word lines
10/26/2000DE19916913A1 Semiconductor memory device with memory banks configuration
10/25/2000EP1047077A1 Nonvolatile memory device with double hierarchical decoding
10/25/2000EP1046172A1 Device containing a multi-port memory
10/24/2000US6138254 Method and apparatus for redundant location addressing using data compression
10/24/2000US6138227 Device for the jump-like addressing of specific lines of a serially operating digital memory
10/24/2000US6138220 Method and device for the predictive reading of a memory
10/24/2000US6137745 Embedded memory control circuit for control of access operations to a memory module
10/24/2000US6137732 Semiconductor memory device having voltage boosting circuit
10/24/2000US6137725 Row decoding circuit for a semiconductor non-volatile electrically programmable memory and corresponding method
10/24/2000US6137328 Clock phase correction circuit
10/24/2000US6137327 Delay lock loop
10/18/2000CN1270393A Dynamic semiconductor memory and semiconductor IC device
10/17/2000US6134637 Data transfer control of a video memory having a multi-divisional random access memory and a multi-divisional serial access memory
10/17/2000US6134181 Configurable memory block
10/17/2000US6134179 Synchronous semiconductor memory device capable of high speed reading and writing
10/17/2000US6134175 Memory address decode array with vertical transistors
10/17/2000US6134174 Semiconductor memory for logic-hybrid memory
10/17/2000US6134173 Programmable logic array integrated circuits
10/17/2000US6134171 Semiconductor integrated circuit device having hierarchical power source arrangement
10/17/2000US6134165 High speed sensing of dual port static RAM cell
10/17/2000US6134154 Semiconductor memory device with several access enabled using single port memory cell
10/17/2000US6134151 Space management for managing high capacity nonvolatile memory
10/17/2000US6134146 Wordline driver for flash electrically erasable programmable read-only memory (EEPROM)
10/12/2000WO2000060605A1 Space management for managing high capacity nonvolatile memory
10/12/2000WO2000031729A8 A digital memory structure and device, and methods for the management thereof
10/12/2000DE10015370A1 Halbleiterspeicherbauelement mit aktivierbaren und deaktivierbaren Wortleitungen Semiconductor memory device with and deactuable word lines
10/11/2000EP1043727A2 Semiconductor device
10/10/2000US6130855 Latching wordline driver for multi-bank memory
10/10/2000US6130854 Programmable address decoder for field programmable memory array
10/10/2000US6130853 Address decoding scheme for DDR memory
10/10/2000US6130844 Low consumption boosted voltage driving circuit
10/10/2000US6130843 Method and circuit for providing a memory device having hidden row access and row precharge times
10/05/2000WO2000031646A3 Data processor integrated circuit with a memory interface unit with programmable strobes to select different memory devices
10/04/2000EP1040483A1 Memory addressing
10/03/2000US6128696 Synchronous memory device utilizing request protocol and method of operation of same
10/03/2000US6128692 Programming and verification address generation for random access memory blocks in programmable logic array integrated circuit devices
10/03/2000US6128247 Semiconductor memory device for making column decoder operable according to RAS access time
10/03/2000US6128246 Semiconductor memory device having write recovery circuit structure
10/03/2000US6128244 Method and apparatus for accessing one of a plurality of memory units within an electronic memory device
10/03/2000US6128209 Semiconductor memory device having dummy bit and word lines
10/03/2000US6126070 IC memory card with security check
09/2000
09/28/2000WO2000026941A9 Word line driver for semiconductor memories
09/27/2000EP1039637A1 Delay line with frequency range trimming
09/27/2000EP1039475A2 Address and data transfer circuit
09/27/2000EP1039470A2 Semiconductor memory device
09/27/2000EP1039369A1 Improved skew pointer generation
09/26/2000US6125388 System for transporting information objects between a user station and multiple remote sources based upon user modifiable object manifest stored in the user station
09/26/2000US6125076 Word line control circuit
09/26/2000US6125075 Semiconductor device incorporating internal power supply for compensating for deviation in operating condition and fabrication process conditions
09/26/2000US6125074 Semiconductor memory device having a small memory cell driving circuit
09/26/2000US6125073 Integrated semiconductor memory
09/26/2000US6125072 Method and apparatus for contiguously addressing a memory system having vertically expanded multiple memory arrays
09/26/2000US6125071 Semiconductor memory device with high data read rate
09/26/2000US6125055 Sector write protect CAMS for a simultaneous operation flash memory
09/26/2000US6125051 Circuit for driving nonvolatile ferroelectric memory
09/26/2000US6124735 Method and apparatus for a N-nary logic circuit using capacitance isolation
09/21/2000WO1998043172A3 Access control system
09/19/2000US6122704 Integrated circuit for identifying an item via a serial port
09/19/2000US6122702 Memory cells matrix for a semiconductor integrated microcontroller
09/19/2000US6122688 Protocol for communication with dynamic memory
09/19/2000US6122221 Scheme for increasing enable access speed in a memory device
09/19/2000US6122218 Multi-port access memory employing a common read/write port
09/19/2000US6122217 Multi-bank memory input/output line selection
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