| Patents for G11C 8 - Arrangements for selecting an address in a digital store (19,368) |
|---|
| 09/26/2001 | EP1054772A4 Memory expansion circuit for ink jet print head identification circuit |
| 09/26/2001 | EP0823117B1 Nonvolatile memory blocking architecture |
| 09/25/2001 | US6295595 Method and structure for accessing a reduced address space of a defective memory |
| 09/25/2001 | US6295227 Non-volatile semiconductor memory device |
| 09/25/2001 | US6295219 Integrated memory |
| 09/20/2001 | WO2001069794A1 Interleave address generator |
| 09/20/2001 | WO2001069606A1 One-shot signal generating circuit |
| 09/20/2001 | US20010023466 Memory device having a programmable register |
| 09/20/2001 | US20010022749 Decoder circuit |
| 09/20/2001 | US20010022748 Virtual channel synchronous dynamic random access memory |
| 09/18/2001 | US6292850 Information storage system including state-designating area on memory card and detecting presence or absence of state-designating member on state-designating area to inhibit or allow writing of information |
| 09/18/2001 | US6292428 Semiconductor device reconciling different timing signals |
| 09/18/2001 | US6292427 Hierarchical sense amp and write driver circuitry for compilable memory |
| 09/18/2001 | US6292413 Semiconductor device, semiconductor memory device and semiconductor integrated circuit device |
| 09/18/2001 | US6292411 Delay control circuit synchronous with clock signal |
| 09/18/2001 | US6292406 Method and low-power circuits used to generate accurate boosted wordline voltage for flash memory core cells in read mode |
| 09/18/2001 | US6292403 Circuit and method for implementing single-cycle read/write operation(s), and random access memory including the circuit and/or practicing the method |
| 09/18/2001 | US6292384 Access structure for high density read only memory |
| 09/18/2001 | US6292017 Programmable logic device incorporating function blocks operable as wide-shallow RAM |
| 09/18/2001 | CA2180421C Multi-port random access memory |
| 09/13/2001 | WO2001006371A8 Improved memory system apparatus and method |
| 09/13/2001 | US20010021143 Circuit, apparatus and method for generating address |
| 09/13/2001 | US20010021140 Semiconductor memory device |
| 09/13/2001 | US20010021131 Semiconductor Device |
| 09/13/2001 | US20010021117 Read-ahead electrically erasable and programmable serial memory |
| 09/13/2001 | US20010020840 Semiconductor integrated circuit |
| 09/11/2001 | US6289468 Technique for controlling system bus timing with on-chip programmable delay lines |
| 09/11/2001 | US6288970 Programmable logic device memory array circuit having combinable single-port memory arrays |
| 09/11/2001 | US6288969 Multi-port random access memory |
| 09/11/2001 | US6288968 Semiconductor integrated circuit exhibiting improved high speed performance without wait time in operation |
| 09/11/2001 | US6288948 Wired address compare circuit and method |
| 09/11/2001 | US6288945 Nonvolatile semiconductor memory device having electrically and collectively erasable characteristics |
| 09/11/2001 | US6288941 Electrically erasable semiconductor non-volatile memory device having memory cell array divided into memory blocks |
| 09/11/2001 | US6288939 Circuit configuration for monitoring states of a memory device |
| 09/11/2001 | US6288937 Decoded generic routing pool |
| 09/11/2001 | US6288925 System with meshed power and signal buses on cell array |
| 09/11/2001 | US6288924 Semiconductor device and process for manufacturing the same |
| 09/11/2001 | US6288601 Boosted potential generating circuit |
| 09/11/2001 | US6288589 Method and apparatus for generating clock signals |
| 09/07/2001 | WO2001065568A1 Trimming method and system for wordline booster to minimize process variation of boosted wordline voltage |
| 09/06/2001 | US20010019513 Semiconductor memory device having stable wordline operations |
| 09/06/2001 | US20010019511 Semiconductor integrated circuit |
| 09/06/2001 | US20010019502 Semiconductor integrated circuit device having hierarchical power source arrangement |
| 09/06/2001 | US20010019139 Circuit configuration for an integrated semiconductor memory with column access |
| 09/05/2001 | EP1130601A1 Column decoder circuit for page reading of a semiconductor memory |
| 09/05/2001 | EP1129409A2 Redundant form address decoder for memory system |
| 09/04/2001 | US6286086 Data protection method for a semiconductor memory and corresponding protected memory device |
| 09/04/2001 | US6285627 Address transition detector architecture for a high density flash memory device |
| 09/04/2001 | US6285618 Device and method for repairing a memory array by storing each bit in multiple memory cells in the array |
| 09/04/2001 | US6285604 Dummy memory cells for high accuracy self-timing circuits in dual-port SRAM |
| 09/04/2001 | US6285594 Wordline voltage protection |
| 09/04/2001 | US6284585 Electronic memory device having bit lines with block selector switches |
| 08/30/2001 | WO2001063618A1 Wordline driver for flash memory read mode |
| 08/30/2001 | US20010017813 Semiconductor memory device |
| 08/30/2001 | US20010017793 PLD with on-chip memory having a shadow |
| 08/30/2001 | US20010017792 Semiconductor storage device conducting a late-write operation and controlling a test read-operation to read data not from a data latch circuit but from a memory core circuit regardless of whether a preceding address and a present address match each other |
| 08/30/2001 | US20010017791 Dynamic random access memory (DRAM) having ATD circuit |
| 08/30/2001 | US20010017788 Semiconductor memory device utilizing access to memory area located outside main memory area |
| 08/30/2001 | US20010017380 Semiconductor integrated circuit |
| 08/30/2001 | DE10104201A1 Mehr-Tor-Registerstruktur, die ein Impulsschreibverfahren verwendet More-port register structure that uses a pulse writing method |
| 08/30/2001 | DE10059486A1 Universaldecodierimplementierung für mehrtorige Speicherarrayschaltungen Universal decoder implementation for multi-port memory array circuits |
| 08/30/2001 | DE10007176A1 Dekodiervorrichtung Decoding |
| 08/29/2001 | EP0830682B1 Auto-activate on synchronous dynamic random access memory |
| 08/28/2001 | US6282149 Circuit and method for synchronized data banking |
| 08/28/2001 | US6282147 Semiconductor memory device having word lines driven by row selecting signal and column selecting signal lines arranged parallel to each other |
| 08/28/2001 | US6282144 Multi-ported memory with asynchronous and synchronous protocol |
| 08/28/2001 | US6282143 Multi-port static random access memory design for column interleaved arrays |
| 08/28/2001 | US6282139 Register file with improved noise immunity and aspect ratio |
| 08/28/2001 | US6282136 Semiconductor memory devices and sensors using the same |
| 08/28/2001 | US6282135 Intializing memory cells within a dynamic memory array prior to performing internal memory operations |
| 08/28/2001 | US6282133 Semiconductor memory device having a delay circuit for generating a read timing |
| 08/28/2001 | US6282131 Self-timed clock circuitry in a multi-bank memory instance using a common timing synchronization node |
| 08/23/2001 | WO2001061705A1 Memory device with support for unaligned access |
| 08/23/2001 | US20010015932 Nonvolatile semiconductor memory device having electrically and collectively erasable characteristics |
| 08/23/2001 | US20010015931 Semiconductor memory device having a plurality of banks sharing a column control unit |
| 08/23/2001 | US20010015659 Logic circuit |
| 08/22/2001 | EP1126467A1 Synchronous counter for electronic memories |
| 08/22/2001 | EP1125301A1 Memory address decoding circuit for a simultaneous operation flash memory device with a flexible bank partition architecture |
| 08/22/2001 | EP1125299A1 A data writing/reading method, a de-interleaving method, a data processing method, a memory and a memory drive apparatus |
| 08/22/2001 | EP0763240B1 Bit map addressing schemes for flash memory |
| 08/21/2001 | US6279071 System and method for column access in random access memories |
| 08/21/2001 | US6279068 Set of two memories on the same monolithic integrated circuit |
| 08/21/2001 | US6278649 Bank selection structures for a memory array, including a flat cell ROM array |
| 08/21/2001 | US6278648 Method for writing to multiple banks of a memory device |
| 08/21/2001 | US6278647 Semiconductor memory device having multi-bank and global data bus |
| 08/21/2001 | US6278645 High speed video frame buffer |
| 08/21/2001 | US6278640 Dynamic memory word line driver scheme |
| 08/21/2001 | US6278628 Semiconductor integrated circuit |
| 08/21/2001 | US6278297 Row decoder with switched power supply |
| 08/16/2001 | US20010014052 Semiconductor integrated circuit device |
| 08/16/2001 | US20010014051 Semiconductor IC device having a memory and a logic circuit implemented with a single chip |
| 08/16/2001 | US20010014050 Semiconductor memory device and bit line connecting method thereof |
| 08/16/2001 | US20010014048 Delay locked loop with delay control unit for noise elimination |
| 08/16/2001 | US20010014046 Semiconductor memory device for fast access |
| 08/16/2001 | US20010014042 Semiconductor device, semiconductor memory device and semiconductor integrated circuit device |
| 08/16/2001 | US20010014041 Synchronous counter for electronic memories |
| 08/16/2001 | US20010013793 Programmable logic device incorporating function blocks operable as wide-shallow ram |
| 08/16/2001 | EP1124231A1 Memory circuit with shorter access time |
| 08/14/2001 | US6275894 Bank selector circuit for a simultaneous operation flash memory device with a flexible bank partition architecture |
| 08/14/2001 | US6275443 Latched row or column select enable driver |