| Patents for G11C 8 - Arrangements for selecting an address in a digital store (19,368) |
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| 03/29/2001 | DE10043650A1 Internal clock generation circuit for SDRAM, has delay circuits to delay internal signals based on delay control time set according to phase difference between one of the internal signals and output of delay circuit |
| 03/27/2001 | US6209071 Asynchronous request/synchronous data dynamic random access memory |
| 03/27/2001 | US6209069 Method and apparatus using volatile lock architecture for individual block locking on flash memory |
| 03/27/2001 | US6209056 Semiconductor memory device having a plurality of bank sections distributed in a plurality of divided memory cell arrays |
| 03/27/2001 | US6208575 Dynamic memory array bit line sense amplifier enabled to drive toward, but stopped before substantially reaching, a source of voltage |
| 03/27/2001 | US6208565 Multi-ported register structure utilizing a pulse write mechanism |
| 03/27/2001 | US6208556 Address transition detect timing architecture for a simultaneous operation flash memory device |
| 03/27/2001 | US6208548 Slave circuit select device which can individually select a plurality of slave circuits with one data bus |
| 03/22/2001 | WO2001020670A1 Connection arrangement for enabling the use of identical chips in 3-dimensional stacks of chips requiring addresses specific to each chip |
| 03/22/2001 | WO2001020612A1 Ram cells having a substantially balanced number of n-mos and p-mos transistors for improving layout areas |
| 03/22/2001 | WO2001020610A1 Architecture, method(s) and circuitry for low power memories |
| 03/22/2001 | WO2001020457A1 Method and apparatus for controlling multi-channel bitstreams |
| 03/22/2001 | CA2384862A1 Architecture, method(s) and circuitry for low power memories |
| 03/21/2001 | EP1085521A1 Non-volatile semiconductor memory |
| 03/21/2001 | EP1084496A1 Method and apparatus for sequential memory addressing |
| 03/20/2001 | US6205530 Address translation unit supporting variable page sizes |
| 03/20/2001 | US6205512 Set of two memories on the same monolithic integrated circuit |
| 03/20/2001 | US6205081 Address generating circuit of semiconductor memory device |
| 03/20/2001 | US6205080 Column decode circuits and apparatus |
| 03/20/2001 | US6205062 CAS latency control circuit |
| 03/20/2001 | US6205044 Decoder connection configuration for memory chips with long bit lines |
| 03/20/2001 | US6204541 Semiconductor memory |
| 03/15/2001 | WO2001018640A1 Organization of blocks within a nonvolatile memory unit to effectively decrease sector write operation time |
| 03/14/2001 | EP0966742A4 Pump control circuit |
| 03/14/2001 | CN1287361A Real-time processing method for flash storage |
| 03/13/2001 | US6202194 Method and apparatus for routing 1 of N signals |
| 03/13/2001 | US6202139 Pipelined data cache with multiple ports and processor with load/store unit selecting only load or store operations for concurrent processing |
| 03/13/2001 | US6201756 Semiconductor memory device and write data masking method thereof |
| 03/13/2001 | US6201741 Storage device and a control method of the storage device |
| 03/13/2001 | US6201735 Electrically erasable and programmable nonvolatile semiconductor memory |
| 03/08/2001 | WO2001016954A1 Pipeline structure of memory for high-fast row-cycle |
| 03/07/2001 | CN1286794A Enhanced word line driver to reduce gate capacitance for low voltage applications |
| 03/06/2001 | US6199153 Method and apparatus for minimizing pincount needed by external memory control chip for multiprocessors with limited memory size requirements |
| 03/06/2001 | US6198687 Semiconductor memory device having a plurality of transfer gates and improved word line and column select timing for high speed write operations |
| 03/06/2001 | US6198686 Memory device having row decoder |
| 03/06/2001 | US6198685 Word-line driving circuit and semiconductor memory device |
| 03/06/2001 | US6198684 Word line decoder for dual-port cache memory |
| 03/06/2001 | US6198682 Hierarchical dynamic memory array architecture using read amplifiers separate from bit line sense amplifiers |
| 03/06/2001 | US6198667 Plural memory banks device that can simultaneously read from or write to all of the memory banks during testing |
| 03/06/2001 | US6198659 Defective address data storage circuit for nonvolatile semiconductor memory device having redundant function and method of writing defective address data |
| 03/06/2001 | US6198649 Semiconductor memory device |
| 03/06/2001 | US6198648 Semiconductor memory device with hierarchical bit line architecture |
| 03/06/2001 | US6198324 Flip flops |
| 03/01/2001 | WO2001015173A1 A data writing/reading method, a de-interleaving method, a data processing method, a memory and a memory drive apparatus |
| 03/01/2001 | WO2001015171A2 Flash memory architecture employing three layer metal interconnect |
| 03/01/2001 | DE10036446A1 Memory address generator for transposition memory used in mobile station for coded image data transmission uses e.g. barrel shifter to create column addresses |
| 03/01/2001 | DE10029887A1 Synchrone Halbleiterspeichervorrichtung The synchronous semiconductor memory device |
| 02/27/2001 | US6195308 Self-timed address decoder for register file and compare circuit of a multi-port cam |
| 02/27/2001 | US6195306 Semiconductor device |
| 02/27/2001 | US6195304 Semiconductor memory device and its refresh address signal generating method adapted to reduce power consumption during refresh operation |
| 02/27/2001 | US6195294 Semiconductor device |
| 02/27/2001 | US6195027 Capacitive precharging and discharging network for converting N bit input into M bit output |
| 02/22/2001 | WO2001013214A1 External storage using nonvolatile semiconductor memory |
| 02/22/2001 | DE10027097A1 Halbleiterspeichervorrichtung und eine solche Halbleiterspeichervorrichtung verwendender Sensor A semiconductor memory device, and such a semiconductor memory device using measuring sensor |
| 02/20/2001 | US6192003 Semiconductor memory device using a relatively low-speed clock frequency and capable of latching a row address and a column address with one clock signal and performing a page operation |
| 02/20/2001 | US6192000 Semiconductor memory device having decreased layout area and method of manufacturing the same |
| 02/20/2001 | US6191999 Semiconductor memory device with reduced power consumption |
| 02/20/2001 | US6191998 Programmable logic device memory array circuit having combinable single-port memory arrays |
| 02/20/2001 | US6191997 Memory burst operations in which address count bits are used as column address bits for one, but not both, of the odd and even columns selected in parallel. |
| 02/20/2001 | US6191992 First-in-first-out storage device including synchronized full-state detention and empty-state detention |
| 02/14/2001 | CN1283871A 半导体器件和存储器模块 Semiconductor devices and memory modules |
| 02/13/2001 | US6188642 Integrated memory having column decoder for addressing corresponding bit line |
| 02/13/2001 | US6188635 Process of synchronously writing data to a dynamic random access memory array |
| 02/13/2001 | US6188634 Semiconductor memory having memory bank decoders disposed symmetrically on a chip |
| 02/13/2001 | US6188633 Multi-port computer register file having shared word lines for read and write ports and storage elements that power down or enter a high-impedance state during write operations |
| 02/13/2001 | US6188632 Dual access memory array |
| 02/13/2001 | US6188630 Semiconductor memory device |
| 02/13/2001 | US6188620 Semiconductor memory device having a redundancy judgment circuit |
| 02/13/2001 | US6188619 Memory device with address translation for skipping failed memory blocks |
| 02/13/2001 | US6188617 Reundancy circuit for semiconductor memories |
| 02/13/2001 | US6188597 Semiconductor memory having sub-select lines cross-connected to sub-decoders |
| 02/13/2001 | US6188595 Memory architecture and addressing for optimized density in integrated circuit package or on circuit board |
| 02/08/2001 | DE10035137A1 Semiconducting memory has control signal generation circuit, set/reset circuit, column address decoder circuit, memory cell field, delay circuit that can alter/vary reset signal delay time |
| 02/07/2001 | EP1074994A1 Semiconductor storage device |
| 02/07/2001 | CN1282918A Memory address producing device, moving station and data read/write method |
| 02/06/2001 | US6185644 Memory system including a plurality of memory devices and a transceiver device |
| 02/06/2001 | US6185150 Clock-synchronous system |
| 02/06/2001 | US6185148 General purpose decode implementation for multiported memory array circuits |
| 02/06/2001 | US6185146 Semiconductor memory device and method for producing the same |
| 02/06/2001 | US6185135 Robust wordline activation delay monitor using a plurality of sample wordlines |
| 02/06/2001 | US6185121 Access structure for high density read only memory |
| 02/06/2001 | US6184928 Method and apparatus for split shift register addressing |
| 02/01/2001 | WO2001008015A1 Recording system, data recording device, memory device, and data recording method |
| 01/31/2001 | EP1073060A1 Single supply voltage nonvolatile memory device with hierarchical row decoding |
| 01/30/2001 | US6182184 Method of operating a memory device having a variable data input length |
| 01/30/2001 | US6181641 Memory device having reduced power requirements and associated methods |
| 01/30/2001 | US6181640 Control circuit for semiconductor memory device |
| 01/30/2001 | US6181637 Memory device |
| 01/30/2001 | US6181636 Output line arrangement structure of row decoding array |
| 01/30/2001 | US6181635 Reduced delay address decoders and decoding methods for integrated circuit memory devices |
| 01/30/2001 | US6181634 Multiple-port semiconductor memory device |
| 01/30/2001 | US6181633 Semiconductor device |
| 01/30/2001 | US6181631 Semiconductor memory device with a reduce access time by devising a layout of a circuit without elaborate modification |
| 01/30/2001 | US6181625 Semiconductor storage memory having a reference voltage generation circuit generating the word line voltage |
| 01/30/2001 | US6181624 Integrated circuit memory having a sense amplifier activated based on word line potentials |
| 01/30/2001 | US6181611 Techniques of isolating and enabling higher speed access of memory cells |
| 01/30/2001 | US6181599 Method for applying variable row BIAS to reduce program disturb in a flash memory storage array |
| 01/30/2001 | US6181596 Method and apparatus for a RAM circuit having N-Nary output interface |
| 01/30/2001 | US6181595 Single ended dual port memory cell |
| 01/25/2001 | WO2001006371A1 Improved memory system apparatus and method |