| Patents for G11C 8 - Arrangements for selecting an address in a digital store (19,368) |
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| 07/12/2001 | US20010007533 Non-volatile semiconductor memory device and semiconductor disk device |
| 07/12/2001 | DE19963502A1 Schaltungsanordnung für einen integrierten Halbleiterspeicher mit Spaltenzugriff Circuitry for an integrated semiconductor memory with column access |
| 07/11/2001 | EP1114461A1 Semiconductor circuit |
| 07/11/2001 | CN1303102A Storage for controlling address buffer by programmable delay |
| 07/10/2001 | US6260107 Processor system using synchronous dynamic memory |
| 07/10/2001 | US6260106 Synchronous data storage system having re-drive circuits for reduced signal line loading |
| 07/10/2001 | US6260097 Method and apparatus for controlling a synchronous memory device |
| 07/10/2001 | US6259651 Method for generating a clock phase signal for controlling operation of a DRAM array |
| 07/10/2001 | US6259648 Methods and apparatus for implementing pseudo dual port memory |
| 07/10/2001 | US6259646 Fast accessing of a memory device |
| 07/10/2001 | US6259642 Semiconductor memory device with reduced sensing noise and sensing current |
| 07/10/2001 | US6259635 Capacitive boosting circuit for the regulation of the word line reading voltage in non-volatile memories |
| 07/10/2001 | US6259631 Row drive circuit equipped with feedback transistors for low voltage flash EEPROM memories |
| 07/05/2001 | US20010007136 Timing signal generating circuit, semiconductor integrated circuit device and semiconductor integrated circuit system to which the timing signal generating circuit is applied, and signal transmission system |
| 07/05/2001 | US20010006479 Read circuit of nonvolatile semiconductor memory |
| 07/05/2001 | US20010006236 Semiconductor memory device having hierarchical wordline structure |
| 07/05/2001 | DE19961517A1 Circuit for supplying negative voltage to word lines of semiconductor memory |
| 07/04/2001 | EP1113449A1 Semiconductor memory device having row-related circuit operating at high speed |
| 07/04/2001 | EP1113448A1 Circuit for an integrated semiconductor memory with row access |
| 07/04/2001 | EP1113447A1 Information storage apparatus and information processing method using the same and connector pin assembly |
| 07/03/2001 | US6256767 Demultiplexer for a molecular wire crossbar network (MWCN DEMUX) |
| 07/03/2001 | US6256262 High speed memory device having different read and write clock signals |
| 07/03/2001 | US6256260 Synchronous semiconductor memory device having input buffers and latch circuits |
| 07/03/2001 | US6256257 Memory device including a burn-in controller for enabling multiple wordiness during wafer burn-in |
| 07/03/2001 | US6256256 Dual port random access memories and systems using the same |
| 07/03/2001 | US6256255 Multi-bank memory input/output line selection |
| 07/03/2001 | US6256254 Semiconductor memory device decoder |
| 07/03/2001 | US6256253 Memory device with support for unaligned access |
| 07/03/2001 | US6256251 Circuit with variable voltage boosting ratios in a memory device |
| 07/03/2001 | US6256238 Semiconductor memory device |
| 07/03/2001 | US6256234 Low skew differential receiver with disable feature |
| 07/03/2001 | US6256233 Distributed signal drivers in arrayable devices |
| 07/03/2001 | US6256221 Arrays of two-transistor, one-capacitor dynamic random access memory cells with interdigitated bitlines |
| 07/03/2001 | US6255869 Method and apparatus for system resource negotiation |
| 07/03/2001 | US6255855 Integrated circuit having a decoder |
| 06/28/2001 | WO2001046988A2 Method and apparatus for routing 1 of n signals |
| 06/28/2001 | US20010005373 Virtual channel DRAM |
| 06/28/2001 | US20010005337 Delay locked loop having fast locking time |
| 06/28/2001 | US20010005324 Memory architecture and addressing for optimized density in integrated circuit package or on circuit board |
| 06/28/2001 | US20010005291 Information storage apparatus and information processing apparatus using the same |
| 06/28/2001 | US20010005148 Semiconductor intergrated circuit having logic circuit comprising transistors with lower threshold voltage values and improved pattern layout |
| 06/28/2001 | US20010005027 Semiconductor memory circuit |
| 06/26/2001 | US6252821 Method and apparatus for memory address decode in memory subsystems supporting a large number of memory devices |
| 06/26/2001 | US6252819 Reduced line select decoder for a memory array |
| 06/26/2001 | US6252818 Apparatus and method for operating a dual port memory cell |
| 06/26/2001 | US6252817 Read only memory with neighboring memory blocks sharing block selection lines |
| 06/26/2001 | US6252807 Memory device with reduced power consumption when byte-unit accessed |
| 06/26/2001 | US6252806 Multi-generator, partial array Vt tracking system to improve array retention time |
| 06/26/2001 | US6252804 Semiconductor integrated circuit, and method of controlling same |
| 06/26/2001 | US6252448 Coincident complementary clock generator for logic circuits |
| 06/26/2001 | US6252425 Method and apparatus for an N-NARY logic circuit |
| 06/21/2001 | DE10049104A1 Address sequencer for synchronous flash memory device, has toggle logic cells with either NAND or NOR gates, for generating toggle logic signals corresponding to even and odd address signals |
| 06/19/2001 | US6249850 Semiconductor memory device and method for copying data stored therein |
| 06/19/2001 | US6249481 Semiconductor memory device |
| 06/19/2001 | US6249479 Semiconductor memory device |
| 06/19/2001 | US6249478 Address input circuit and semiconductor memory using the same |
| 06/19/2001 | US6249477 Semiconductor memory device |
| 06/19/2001 | US6249463 Address latch enable signal control circuit for electronic memories |
| 06/14/2001 | WO2001043287A1 Method and apparatus for an n-nary logic circuit |
| 06/14/2001 | WO2001043137A1 Method and system for adaptively adjusting control signal timing in a memory device |
| 06/14/2001 | WO2001043136A1 High performance cmos word-line driver |
| 06/14/2001 | US20010003513 Methods to reduce the effects of leakage current for dynamic circuit elements |
| 06/13/2001 | EP1105877A2 Memory system |
| 06/13/2001 | EP1105875A1 On-chip word line voltage generation for dram embedded in logic process |
| 06/13/2001 | CN1299136A Integrated accessor |
| 06/12/2001 | US6247138 Timing signal generating circuit, semiconductor integrated circuit device and semiconductor integrated circuit system to which the timing signal generating circuit is applied, and signal transmission system |
| 06/12/2001 | US6246633 Semiconductor memory device permitting stabilized operation and high-speed access |
| 06/12/2001 | US6246632 Column decode circuits and apparatus |
| 06/12/2001 | US6246631 Semiconductor memory device |
| 06/12/2001 | US6246630 Intra-unit column address increment system for memory |
| 06/12/2001 | US6246629 Semiconductor IC device having a memory and a logic circuit implemented with a single chip |
| 06/12/2001 | US6246628 Semiconductor memory device having read/write amplifiers disposed for respective memory segments |
| 06/12/2001 | US6246625 Semiconductor integrated circuit device having hierarchical power source arrangement |
| 06/12/2001 | US6246624 Voltage detection circuit power-on/off reset circuit and semiconductor device |
| 06/12/2001 | US6246620 Semiconductor memory device |
| 06/12/2001 | US6246609 Decoder circuit |
| 06/07/2001 | WO2001041149A1 Semiconductor storage and method for testing the same |
| 06/07/2001 | WO2001040947A1 Fuse latch having multiplexers with reduced sizes and lower power consumption |
| 06/07/2001 | US20010003200 Semiconductor storage device |
| 06/07/2001 | US20010002883 Semiconductor device including a repetitive pattern |
| 06/05/2001 | US6243320 Synchronous semiconductor memory device capable of selecting column at high speed |
| 06/05/2001 | US6243319 Semiconductor memory equipped with row address decoder having reduced signal propagation delay time |
| 06/05/2001 | US6243318 Decoder circuit |
| 06/05/2001 | US6243317 Semiconductor memory device which activates column lines at high speed |
| 06/05/2001 | US6243316 Voltage boost reset circuit for a flash memory |
| 06/05/2001 | US6243287 Distributed decode system and method for improving static random access memory (SRAM) density |
| 05/31/2001 | WO2001039194A1 Single-event upset hardened reconfigurable bi-stable cmos latch |
| 05/31/2001 | US20010002177 Semiconductor device |
| 05/30/2001 | CN1297566A Semiconductor storage device |
| 05/29/2001 | US6240046 Integrated circuit random access memory capable of reading either one or more than one data word in a single clock cycle |
| 05/29/2001 | US6240044 High speed address sequencer |
| 05/29/2001 | US6240041 Signal generator with timing margin by using control signal to control different circuit |
| 05/29/2001 | US6240039 Semiconductor memory device and driving signal generator therefor |
| 05/29/2001 | US6240038 Low area impact technique for doubling the write data bandwidth of a memory array |
| 05/29/2001 | US6240006 Semiconductor memory device having reduced interconnection resistance |
| 05/29/2001 | US6239647 Decoder circuit and decoding method of the same |
| 05/29/2001 | US6239495 Multichip semiconductor device and memory card |
| 05/25/2001 | WO2001037090A1 A memory expansion module with stacked memory packages |
| 05/23/2001 | DE19954889A1 Decoder element e.g. for word-line decoder of integrated store |
| 05/22/2001 | US6237104 Method and a related circuit for adjusting the duration of a synchronization signal ATD for timing the access to a non-volatile memory |