| Patents for G11C 8 - Arrangements for selecting an address in a digital store (19,368) |
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| 01/25/2001 | DE10015253A1 Semiconducting memory device has memory cell arrangement with even, odd numbered cell blocks, address generator, odd, even column decoder, masking control signal and data generators |
| 01/24/2001 | CN1281250A DC degradated word line activating timing with self refreshed DRAM |
| 01/23/2001 | US6178490 Method and device for the incremental reading of a memory |
| 01/23/2001 | US6178139 Semiconductor memory device comprised of a double data rate-synchronous dynamic random access memory |
| 01/23/2001 | US6178138 Asynchronously addressable clocked memory device and method of operating same |
| 01/23/2001 | US6178137 Clock-synchronizing semiconductor memory device |
| 01/23/2001 | US6178135 Multi-bank memory devices having bank selection switches therein that enable efficient sense amplifier utilization |
| 01/23/2001 | US6178133 Method and system for accessing rows in multiple memory banks within an integrated circuit |
| 01/23/2001 | US6178129 Separate output power supply to reduce output noise for a simultaneous operation |
| 01/23/2001 | US6178122 Boosted-voltage drive circuit operable with high reliability and semiconductor memory device employing the same |
| 01/16/2001 | US6175535 Cycle control circuit for extending a cycle period of a dynamic memory device subarray |
| 01/16/2001 | US6175533 Multi-port memory cell with preset |
| 01/16/2001 | US6175532 Fast accessible dynamic type semiconductor memory device |
| 01/11/2001 | DE19929725A1 Integrated circuit, SGRAM and decoder unit |
| 01/11/2001 | DE19929172A1 Integrated memory, double data rate DRAM |
| 01/11/2001 | DE10032122A1 Semiconducting memory component with redundancy circuit has temporary memory cells on data lines for replacing faulty cells in memory blocks in response to faulty cell addresses |
| 01/10/2001 | CN1279808A Programmable access protection in a flash memory device |
| 01/09/2001 | US6173432 Method and apparatus for generating a sequence of clock signals |
| 01/09/2001 | US6173217 Method and apparatus to control core logic temperature |
| 01/09/2001 | US6172933 Redundant form address decoder for memory system |
| 01/09/2001 | US6172931 Semiconductor memory device with a multi-bank structure |
| 01/09/2001 | US6172922 Semiconductor memory device having a single transistor two functions as a GND/Y selecting transistor and a precharge selecting transistor |
| 01/09/2001 | US6172915 Unified erase method in flash EEPROM |
| 01/09/2001 | US6172687 Memory device and video image processing apparatus using the same |
| 01/09/2001 | US6172531 Low power wordline decoder circuit with minimized hold time |
| 01/09/2001 | US6172530 Decoder for generating N output signals from two or more precharged input signals |
| 01/04/2001 | WO2001001450A2 Dram cell fabrication process and method for operating same |
| 01/03/2001 | EP1065668A1 Erasing and parallel rewriting circuit for memory cell blocks, particularly for analog flash cells, and related operating method |
| 01/03/2001 | CN1278938A Secure memory having anti-wire tapping |
| 01/03/2001 | CN1278674A Microreglation of frequency range for delay line |
| 01/03/2001 | CN1278646A Synchrnous semi-conductor storage |
| 01/02/2001 | US6169703 Method for controlling high speed digital electronic memory |
| 01/02/2001 | US6169702 Memory device having a chip select speedup feature and associated methods |
| 01/02/2001 | US6169700 Wait state generator circuit and method to allow asynchronous, simultaneous access by two processors |
| 01/02/2001 | US6169423 Method and circuit for regulating the length of an ATD pulse signal |
| 12/27/2000 | EP1063653A1 Nonvolatile memory device, in particular of flash type |
| 12/26/2000 | US6167499 Memory space compression technique for a sequentially accessible memory |
| 12/26/2000 | US6167487 Multi-port RAM having functionally identical ports |
| 12/26/2000 | US6166993 Synchronous semiconductor memory device |
| 12/26/2000 | US6166990 Clock reproduction circuit that can reproduce internal clock signal correctly in synchronization with external clock signal |
| 12/26/2000 | US6166989 Clock synchronous type semiconductor memory device that can switch word configuration |
| 12/26/2000 | US6166988 Semiconductor memory device using one common address bus line between address buffers and column predecoder |
| 12/26/2000 | US6166987 Nonvolatile semiconductor memory device having row decoder |
| 12/26/2000 | US6166975 Dynamic random access memory |
| 12/26/2000 | US6166946 System and method for writing to and reading from a memory cell |
| 12/21/2000 | WO2000077791A1 Method and apparatus for decreasing block write operation times performed on nonvolatile memory |
| 12/20/2000 | EP1061525A1 Row decoder for a nonvolatile memory with possibility of selectively biasing word lines to positive or negative voltages |
| 12/19/2000 | US6163498 Methods and systems for column line selection in a memory device |
| 12/19/2000 | US6163497 Semiconductor memory device |
| 12/19/2000 | US6163495 Architecture, method(s) and circuitry for low power memories |
| 12/19/2000 | US6163489 Semiconductor memory having multiple redundant columns with offset segmentation boundaries |
| 12/19/2000 | US6163481 Flash memory wordline tracking across whole chip |
| 12/19/2000 | US6163475 Bit line cross-over layout arrangement |
| 12/19/2000 | US6161916 Memory expansion circuit for ink jet print head identification circuit |
| 12/14/2000 | DE19946201C1 Voltage buffering arrangement in dynamic CMOS memory, i.e. DRAM |
| 12/13/2000 | EP1058930A1 A memory supporting multiple address protocols |
| 12/12/2000 | US6160755 Clock signal from an adjustable oscillator for an integrated circuit |
| 12/12/2000 | US6160753 Semiconductor integrated circuit device having main word lines and sub-word lines |
| 12/12/2000 | US6160752 Semiconductor memory device |
| 12/12/2000 | US6160751 Semiconductor memory device allowing efficient column selection |
| 12/12/2000 | US6160749 Pump control circuit |
| 12/12/2000 | US6160747 Configuration for crosstalk attenuation in word lines of DRAM circuits |
| 12/12/2000 | US6160736 Memory circuit for changing boost ratio |
| 12/12/2000 | US6160733 Low voltage and low power static random access memory (SRAM) |
| 12/12/2000 | US6160730 Multi-block memory |
| 12/07/2000 | DE19729579C2 Verfahren zum Aktivieren einer redundanten Wortleitung bei Inter-Segment-Redundanz bei einem Halbleiterspeicher mit in Segmenten organisierten Wortleitungen A method for activating a redundant word line at Inter-segment redundancy in a semiconductor memory organized in segments of word lines |
| 12/06/2000 | EP1058271A1 CMOS switch circuit for transferring high voltages, in particular for line decoding in nonvolatile memories, with reduced consumption during switching |
| 12/06/2000 | EP1058267A2 Semiconductor memory |
| 12/06/2000 | EP1058192A2 EEPROM with redundancy |
| 12/05/2000 | US6157990 Independent chip select for SRAM and DRAM in a multi-port RAM |
| 12/05/2000 | US6157983 Concurrent write of multiple chunks of data into multiple subarrays of flash EEPROM |
| 12/05/2000 | US6157590 Solid state memory having a latch circuit |
| 12/05/2000 | US6157569 Non-volatile semiconductor memory |
| 12/05/2000 | US6157225 Driving circuit with three output levels, one output level being a boosted level |
| 11/30/2000 | WO2000026941A3 Word line driver for semiconductor memories |
| 11/29/2000 | EP1055178A2 Data processor integrated circuit with a memory interface unit with programmable strobes to select different memory devices |
| 11/29/2000 | EP1055176A2 Access control system |
| 11/29/2000 | EP1054772A2 Memory expansion circuit for ink jet print head identification circuit |
| 11/28/2000 | US6154416 Column address decoder for two bit prefetch of semiconductor memory device and decoding method thereof |
| 11/28/2000 | US6154415 Internal clock generation circuit of semiconductor device and method for generating internal clock |
| 11/28/2000 | US6154414 Semiconductor memory device having a plurality of memory blocks |
| 11/28/2000 | US6154403 Semiconductor memory device |
| 11/28/2000 | US6154395 Semiconductor memory device having a layout pattern adjusted input terminal capacitance |
| 11/28/2000 | US6154389 Semiconductor memory device with a column redundancy occupying a less chip area |
| 11/28/2000 | US6154120 Method and apparatus for an N-nary equality comparator |
| 11/28/2000 | US6154062 Semiconductor integrated circuits with power reduction mechanism |
| 11/28/2000 | US6154056 Tri-stating address input circuit |
| 11/28/2000 | US6153468 Method of forming a logic array for a decoder |
| 11/23/2000 | WO2000070620A1 Memory array with address scrambling |
| 11/23/2000 | DE19922155A1 Memory arrangement and memory access procedure for microcomputers has an additional scrambling step to increase data security, for use in financial applications etc. |
| 11/23/2000 | DE19921868A1 Redundant semiconductor memory circuit |
| 11/23/2000 | DE10016986A1 Halbleiterspeicherbauelement und Verfahren zur Lese-/Schreibsteuerung hierfür The semiconductor memory device and method for reading / writing control for this |
| 11/21/2000 | US6151273 Synchronous semiconductor memory device |
| 11/21/2000 | US6151271 Integrated circuit memory devices having data selection circuits therein which are compatible with single and dual rate mode operation and methods of operating same |
| 11/21/2000 | US6151267 Memory device with decoder having simplified structure |
| 11/21/2000 | US6151266 Asynchronous multiport register file with self resetting write operation |
| 11/21/2000 | US6151258 Programmable logic device with multi-port memory |
| 11/21/2000 | US6151247 Method and apparatus for decreasing block write operation times performed on nonvolatile memory |
| 11/21/2000 | US6151036 Large capacity data storage device |
| 11/21/2000 | US6149316 Flash EEprom system |