| Patents for G11C 8 - Arrangements for selecting an address in a digital store (19,368) |
|---|
| 03/21/2002 | WO2002023548A2 Combined tracking of wll and vpp with low threshold voltage in dram array |
| 03/21/2002 | WO2001075895A3 Elimination of precharge operation in synchronous flash memory |
| 03/21/2002 | US20020034118 Integrated memory and memory configuration with a plurality of memories and method of operating such a memory configuration |
| 03/21/2002 | US20020034115 Semiconductor memory device having fixed CAS latency in normal operation and various CAS latencies in test mode |
| 03/21/2002 | US20020033810 Display driver IC |
| 03/21/2002 | US20020033489 Semiconductor device |
| 03/21/2002 | DE10054520C1 Data memory with several databanks has respective column control devices for different databanks arranged in common plane extending in row direction |
| 03/20/2002 | EP1189235A1 Variable slew rate output driver for high speed, low voltage non-volatile memory |
| 03/20/2002 | EP1189139A1 Recording system, data recording device, memory device, and data recording method |
| 03/20/2002 | CN1340867A 磁阻元件 Magnetoresistive element |
| 03/20/2002 | CN1340823A Word line electronic drive circuit of memory matrix and memory equipment |
| 03/20/2002 | CN1340822A Serial memory |
| 03/19/2002 | US6360341 Editing apparatus and generating method for physical conversion definition |
| 03/19/2002 | US6360307 Circuit architecture and method of writing data to a memory |
| 03/19/2002 | US6360295 Serially loadable digital electronic memory and method of loading the same |
| 03/19/2002 | US6359973 Data access arrangement utilizing a serialized digital data path across an isolation barrier |
| 03/19/2002 | US6359828 Column address decoder and decoding method for controlling column select line enable time |
| 03/19/2002 | US6359827 Method of constructing a very wide, very fast distributed memory |
| 03/19/2002 | US6359826 Method and a system for controlling a data sense amplifier for a memory chip |
| 03/19/2002 | US6359824 Activation of wordline decoders to transfer a high voltage supply |
| 03/19/2002 | US6359813 Semiconductor memory device having improved data transfer rate without providing a register for holding write data |
| 03/19/2002 | US6359803 Semiconductor memory device that can access two regions alternately at high speed |
| 03/19/2002 | US6359801 Low power memory module using restricted RAM activation |
| 03/14/2002 | US20020032843 Device and method for controlling solid-state memory system |
| 03/14/2002 | US20020032830 Memory unit and buffer access control circuit for updating an address when consecutively accessing upper and lower buffers |
| 03/14/2002 | US20020031040 Semiconductor device including memory with reduced current consumption |
| 03/14/2002 | US20020031038 Semiconductor device that enables simultaneous read and write/read operation |
| 03/14/2002 | US20020031035 Multi-bank semiconductor memory device |
| 03/14/2002 | US20020031034 Semiconductor memory |
| 03/14/2002 | US20020031024 Semiconductor device having redundancy circuit |
| 03/14/2002 | US20020031022 Semiconductor memory having multiple redundant columns with offset segmentation boundaries |
| 03/14/2002 | US20020031006 Semiconductor memory device having improved memory cell and bit line pitch |
| 03/14/2002 | DE10144247A1 Semiconducting memory component has clock buffer that outputs first and second internal clock signals with lower frequency than and same frequency as external clock signal |
| 03/14/2002 | DE10041688A1 Integrierter Speicher mit Speicherzellen in mehreren Speicherzellenblöcken und Verfahren zum Betrieb eines solchen Speichers Integrated memory having memory cells in a plurality of memory cell blocks and method for operating such a memory, |
| 03/14/2002 | DE10038925A1 Elektronische Treiberschaltung für Wortleitungen einer Speichermatrix und Speichervorrichtung Electronic driver circuit for word lines of a memory array and memory device |
| 03/14/2002 | DE10038665C1 Schaltungsanordnung zum Deaktivieren von Wortleitungen einer Speichermatrix Circuitry to disable word lines of a memory matrix |
| 03/13/2002 | EP1187339A1 Interleave address generator |
| 03/13/2002 | EP0793847B1 Register file read/write cell |
| 03/13/2002 | CN2482190Y Internal storage configuration |
| 03/12/2002 | US6356508 Semiconductor storage device |
| 03/12/2002 | US6356506 Full page increment/decrement burst for DDR SDRAM/SGRAM |
| 03/12/2002 | US6356505 Internal regeneration of the address latch enable (ALE) signal of a protocol of management of a burst interleaved memory and related circuit |
| 03/12/2002 | US6356504 Address generating and decoding circuit for use in a burst-type and high-speed random access memory device which has a single data rate and a double data rate scheme |
| 03/12/2002 | US6356503 Reduced latency row selection circuit and method |
| 03/12/2002 | US6356502 Address strobe signal generator for memory device |
| 03/12/2002 | US6356500 Reduced power DRAM device and method |
| 03/12/2002 | US6356489 Integrated circuit memory devices having circuits therein that preserve minimum /RAS TO /CAS Delays |
| 03/12/2002 | US6356485 Merging write cycles by comparing at least a portion of the respective write cycle addresses |
| 03/12/2002 | US6356484 Semiconductor memory device |
| 03/12/2002 | US6356481 Row decoder for a nonvolatile memory with capability of selectively biasing word lines to positive or negative voltages |
| 03/12/2002 | US6356473 Static random access memory (SRAM) |
| 03/12/2002 | US6356108 Programmable logic device incorporating function blocks operable as wide-shallow RAM |
| 03/07/2002 | WO2002019342A1 Nonvolatile memory |
| 03/07/2002 | WO2002019335A2 Word line decoding architecture in a flash memory |
| 03/07/2002 | US20020029317 Processor system using synchronous dynamic memory |
| 03/07/2002 | US20020027829 Synchronous semiconductor memory apparatus and input information latch control method thereof |
| 03/07/2002 | US20020027828 Semiconductor device with reduced error operation caused by threshold voltage variation |
| 03/07/2002 | US20020027827 Circuit configuration for deactivating word lines in a memory matrix |
| 03/07/2002 | US20020027826 Column decoding apparatus for use in a semiconductor memory device |
| 03/07/2002 | US20020027824 Method for writing to multiple banks of a memory device |
| 03/07/2002 | US20020027823 Semiconductor memory device |
| 03/07/2002 | US20020027264 MOSFET technology for programmable address decode and correction |
| 03/06/2002 | EP1184870A1 Electronic driving circuit for memory word lines and memory device |
| 03/06/2002 | EP1184869A2 Data storage device and data storing method |
| 03/06/2002 | EP1183690A1 Memory array with address scrambling |
| 03/06/2002 | EP0840928B1 An integrated circuit having enable control circuitry |
| 03/05/2002 | US6353572 Semiconductor integrated circuit |
| 03/05/2002 | US6353552 PLD with on-chip memory having a shadow register |
| 02/28/2002 | WO2002017326A1 High performance embedded semiconductor memory device with multiple dimension first-level bit-lines |
| 02/28/2002 | WO2002017324A1 Integrated memory comprising memory locations in several memory location blocks, and method for operating a memory of this type |
| 02/28/2002 | WO2001075896A3 Flash with consistent latency for read operations |
| 02/28/2002 | US20020026600 Integrated circuit memory systems having programmable signal buffers for adjusting signal transmission delays and methods of operating same |
| 02/28/2002 | US20020026599 Semiconductor memory device achieving faster operation based on earlier timings of latch operations |
| 02/28/2002 | US20020026557 Semiconductor circuit with address translation circuit that enables quick serial access in row or column directions |
| 02/28/2002 | US20020024878 Circuit for generating address of semiconductor memory device |
| 02/28/2002 | US20020024877 Latched column select enable driver |
| 02/28/2002 | US20020024876 Semiconductor integrated circuit for which high voltage countermeasure was taken |
| 02/28/2002 | US20020024874 Method of constructing a very wide, very fast distributed memory |
| 02/28/2002 | US20020024872 Full page increment/decrement burst for DDR SDRAM/SGRAM |
| 02/28/2002 | US20020024871 Semiconductor memory device and layout method thereof |
| 02/28/2002 | US20020024870 Semiconductor memory device with shorter signal lines |
| 02/28/2002 | US20020024869 Semiconductor device |
| 02/28/2002 | US20020024852 Semiconductor memory and method of operating same |
| 02/28/2002 | US20020024849 Nonvolatile semiconductor memory |
| 02/28/2002 | US20020024848 Nonvolatile semiconductor memory |
| 02/28/2002 | US20020024847 Semiconductor device having memory |
| 02/28/2002 | US20020024834 Memory module having programmable logic device and sTSOP |
| 02/28/2002 | US20020024832 Semiconductor memory device |
| 02/28/2002 | US20020024064 Method of designing semiconductor integrated circuit device and semiconductor integrated circuit device |
| 02/28/2002 | US20020024059 MIS semiconductor device having improved gate insulating film reliability |
| 02/28/2002 | US20020024049 Semiconductor storage apparatus |
| 02/27/2002 | EP1182713A2 Magneto-resistive element |
| 02/27/2002 | EP1182666A1 Integrated memory with magnetoresistive memory cells |
| 02/27/2002 | EP1182664A2 Memory matrix word line de-assertion circuit |
| 02/27/2002 | EP0943146B1 Bi-directional shift register |
| 02/27/2002 | EP0815561B1 Optimization circuitry and control for a synchronous memory device preferably with programmable latency period |
| 02/27/2002 | CN1338105A Improved word line boost circuit |
| 02/27/2002 | CN1337707A Semiconductor storage apparatus for increasing bus efficiency and storage system |
| 02/26/2002 | US6351434 Synchronous counter for electronic memories |
| 02/26/2002 | US6351433 Semiconductor memory device employing pipeline operation with reduced power consumption |