| Patents for G11C 8 - Arrangements for selecting an address in a digital store (19,368) |
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| 10/01/2002 | US6459647 Split-bank architecture for high performance SDRAMs |
| 10/01/2002 | US6459646 Bank-based configuration and reconfiguration for programmable logic in a system on a chip |
| 10/01/2002 | US6459645 VPX bank architecture |
| 10/01/2002 | US6459644 Semiconductor memory device with block alignment function |
| 10/01/2002 | US6459643 Semiconductor integrated circuit |
| 10/01/2002 | US6459641 Semiconductor memory device |
| 10/01/2002 | US6459619 Non-volatile semiconductor memory device for selectively re-checking word lines |
| 10/01/2002 | US6459617 Method and circuitry for bank tracking in write command sequence |
| 10/01/2002 | US6459303 High speed programmable address decoder |
| 10/01/2002 | US6459301 Semiconductor circuit device having active and standby states |
| 09/26/2002 | WO2002075812A1 Method of producing semiconductor integrated circuit device and semiconductor integrated circuit device |
| 09/26/2002 | US20020138688 Memory array with dual wordline operation |
| 09/26/2002 | US20020138243 Semiconductor integrated circuit device |
| 09/26/2002 | US20020136082 Semiconductor memory device including standby mode for reducing current consumption of delay locked loop |
| 09/26/2002 | US20020136080 Method and apparatus for invalidating memory array write operations |
| 09/26/2002 | US20020136076 Memory device and method for sensing while programming a non-volatile memory cell |
| 09/26/2002 | US20020136062 Memory array organization for static arrays |
| 09/26/2002 | US20020136061 Method and memory system for writing in data |
| 09/26/2002 | US20020136059 Method and system for increasing programming bandwidth in a non-volatile memory device |
| 09/26/2002 | US20020136057 Nonvolatile semiconductor memory device having electrically and collectively erasable characteristics |
| 09/26/2002 | US20020136047 Method and apparatus for biasing selected and unselected array lines when writing a memory array |
| 09/26/2002 | US20020136045 Memory device with row and column decoder circuits arranged in a checkerboard pattern under a plurality of memory arrays |
| 09/26/2002 | US20020135413 Stabilized delay circuit |
| 09/26/2002 | US20020135397 Semiconductor integrated circuits with power reduction mechanism |
| 09/26/2002 | DE10114443A1 Writing data involves feeding address in before data item, temporarily storing it then passing it to address decoder after delay; address and data item are almost simultaneously fed to decoder |
| 09/26/2002 | DE10111454A1 Memory arrangement for computer has memory cell field, decoder circuit with word, bit line decoders, read output for reading from individual cells by selecting corresponding word, bit lines |
| 09/25/2002 | EP1244110A2 Protocol for communication with dynamic memory |
| 09/25/2002 | EP1242868A1 Organization of blocks within a nonvolatile memory unit to effectively decrease sector write operation time |
| 09/25/2002 | EP0968608B1 Receiver/decoder and method of reception |
| 09/24/2002 | US6456563 Semiconductor memory device that operates in sychronization with a clock signal |
| 09/24/2002 | US6456559 Semiconductor integrated circuit |
| 09/24/2002 | US6456558 Column decoding apparatus for use in a semiconductor memory device |
| 09/24/2002 | US6456557 Voltage regulator for memory device |
| 09/24/2002 | US6456555 Voltage detecting circuit for semiconductor memory device |
| 09/24/2002 | US6456538 Nonvolatile memory, system having nonvolatile memories, and data read method of the system |
| 09/24/2002 | US6456530 Nonvolatile memory device with hierarchical sector decoding |
| 09/24/2002 | US6456119 Decoding apparatus |
| 09/24/2002 | US6456118 Decoder circuit |
| 09/19/2002 | US20020133731 Duty cycle distortion compensation for the data output of a memory device |
| 09/19/2002 | US20020131320 SRAM emulator |
| 09/19/2002 | US20020131318 Semiconductor device including multi-chip |
| 09/19/2002 | US20020131317 Method and apparatus for off boundary memory access |
| 09/19/2002 | US20020131315 Multi-bank memory |
| 09/19/2002 | US20020131314 Semiconductor device incorporating internal power supply for compensating for deviation in operating condition and fabrication process conditions |
| 09/19/2002 | US20020131296 Magnetic material memory and information reproducing method of the same |
| 09/19/2002 | US20020131291 Interleaved wordline architecture |
| 09/19/2002 | US20020131290 Device and method to reduce wordline RC time constant in semiconductor memory devices |
| 09/19/2002 | US20020130681 Programmable logic array integrated circuits |
| 09/19/2002 | US20020130248 Circuit arrangement and method of protecting at least a chip arrangement from manipulation and/or abuse |
| 09/19/2002 | DE10110624A1 Integrated memory with two memory regions and data bus |
| 09/19/2002 | DE10110274A1 Integrierter Speicher mit mehreren Speicherzellenfeldern Integrated memory having a plurality of memory cell arrays |
| 09/18/2002 | EP0757353B1 Multi-port random access memory |
| 09/17/2002 | US6453400 Semiconductor integrated circuit device |
| 09/17/2002 | US6452869 Address broadcasting to a paged memory device to eliminate access latency penalty |
| 09/17/2002 | US6452868 Method for generating memory addresses for accessing memory-cell arrays in memory devices |
| 09/17/2002 | US6452867 Full page increment/decrement burst for DDR SDRAM/SGRAM |
| 09/17/2002 | US6452864 Interleaved memory device for sequential access synchronous reading with simplified address counters |
| 09/17/2002 | US6452863 Method of operating a memory device having a variable data input length |
| 09/17/2002 | US6452862 Semiconductor memory device having hierarchical word line structure |
| 09/17/2002 | US6452861 Semiconductor memory device allowing simultaneous inputting of N data signals |
| 09/17/2002 | US6452859 Dynamic semiconductor memory device superior in refresh characteristics |
| 09/17/2002 | US6452858 Semiconductor device |
| 09/17/2002 | US6452857 Circuits for controlling the storage of data into memory |
| 09/17/2002 | US6452828 Dynamic random access memory (DRAM) having a structure for emplying a word line low voltage |
| 09/17/2002 | US6452432 Signal processing circuits having a pair of delay locked loop (DLL) circuits for adjusting a duty-cycle of a periodic digital signal and methods of operating same |
| 09/14/2002 | CA2340985A1 Interleaved wordline architecture |
| 09/14/2002 | CA2340804A1 Sram emulator |
| 09/12/2002 | WO2002071407A2 Asynchronous, high-bandwidth memory component using calibrated timing elements |
| 09/12/2002 | WO2001015171A3 Flash memory architecture employing three layer metal interconnect |
| 09/12/2002 | US20020129249 Smartcard for use with a receiver of encrypted broadcast signals, and receiver |
| 09/12/2002 | US20020129219 Method and device for sequential readout of a memory with address jump |
| 09/12/2002 | US20020129094 Software and method for automatically sending a data object that includes user demographics |
| 09/12/2002 | US20020129071 Pseudo random address generator for 0.75M cache |
| 09/12/2002 | US20020126806 Data access arrangement utilizing a serialized digital data path across an isolation barrier |
| 09/12/2002 | US20020126566 Semiconductor integrated circuit |
| 09/12/2002 | US20020126563 Interleaved memory device for sequential access synchronous reading with simplified address counters |
| 09/12/2002 | US20020126562 Memory circuitry for programmable logic integrated circuit devices |
| 09/12/2002 | US20020126540 Multiplexer with dummy switches in normally off state to increase operating speed |
| 09/12/2002 | US20020126539 Non-volatile memory device with erase address register |
| 09/12/2002 | US20020125585 Very small swing high performance asynchronous CMOS static memory (multi-port register file) with power reducing column multiplexing scheme |
| 09/11/2002 | EP1239490A2 Integrated circuit for storage and retrieval of multiple digital bits per nonvolatile memory cell |
| 09/11/2002 | EP1238394A1 Method and apparatus for improving cell life of sequential counters stored in non-volatile memory |
| 09/11/2002 | CN1368734A Semiconductor memory capable of control work timing of read amplifier |
| 09/10/2002 | US6449681 Memory unit and buffer access control circuit for updating an address when consecutively accessing upper and lower buffers |
| 09/10/2002 | US6449213 Memory interface having source-synchronous command/address signaling |
| 09/10/2002 | US6449211 Voltage driver for a memory |
| 09/10/2002 | US6449210 Semiconductor memory array architecture |
| 09/10/2002 | US6449209 Semiconductor memory device comprising more than two internal banks of different sizes |
| 09/10/2002 | US6449194 Multiplexer with dummy switches in normally off state to increase operating speed |
| 09/10/2002 | US6449193 Burst access memory system |
| 09/10/2002 | US6449192 Programmable read-only memory generating identical word-line voltages from different power-supply voltages |
| 09/10/2002 | US6448607 Nonvolatile memory having embedded word lines |
| 09/10/2002 | US6448601 Memory address and decode circuits with ultra thin body transistors |
| 09/06/2002 | WO2002069496A2 Differential input buffer bias pulser |
| 09/06/2002 | WO2002069342A2 Method and apparatus for off boundary memory access |
| 09/06/2002 | WO2002019335A3 Word line decoding architecture in a flash memory |
| 09/06/2002 | CA2438693A1 Method and apparatus for off boundary memory access |
| 09/05/2002 | US20020124130 Memory controller and method using logical/physical address control table |
| 09/05/2002 | US20020124055 Software and method for automatically pre-fetching additional data objects referenced by a first data object |
| 09/05/2002 | US20020122349 Semiconductor integrated circuit for successively scanning lines of electrodes of an image display apparatus |