Patents
Sitemap › G11 - Information storage › G11C - Static stores › G11C 8 - Arrangements for selecting an address in a digital store
Patents for G11C 8 - Arrangements for selecting an address in a digital store (19,368)
01/2003
01/02/2003US20030002379 Low power architecture for register files
01/02/2003US20030002377 Semiconductor memory device, information apparatus, and method for determining access period for semiconductor memory device
01/02/2003US20030002371 Auto precharge apparatus having autoprecharge gapless function protecting circuit in semiconductor memory device
01/02/2003US20030002358 Semiconductor memory device capable of adjusting the number of banks and method for adjusting the number of banks
01/02/2003US20030002352 Circuit for clamping word-line voltage
01/02/2003US20030002338 Biasing scheme of floating unselected wordlines and bitlines of a diode-based memory array
01/02/2003US20030001635 Clock synchronization circuit
01/02/2003US20030001181 Method of fabricating a DRAM cell having a thin dielectric access transistor and a thick dielectric storage capacitor
01/02/2003EP1271540A2 Semiconductor memory device, information apparatus, and method for determining access period for semiconductor memory device
01/02/2003EP1269476A2 Synchronous flash memory
01/02/2003EP1269475A1 Multidimensional addressing architecture for electronic devices
01/02/2003EP1269473A2 Synchronous flash memory with non-volatile mode register
01/02/2003EP1269472A2 Elimination of precharge operation in synchronous flash memory
01/02/2003EP1034463A4 Method and apparatus for audibly indicating when a predetermined location has been encountered in stored data
12/2002
12/31/2002US6501702 Semiconductor memory integrated circuit
12/31/2002US6501701 Semiconductor memory device
12/31/2002US6501700 Internal addressing structure of a semiconductor memory
12/31/2002US6501686 Electronic driver circuit for word lines in a memory matrix, and memory apparatus
12/31/2002US6501675 Alternating reference wordline scheme for fast DRAM
12/31/2002US6501672 Dynamic random access memory (DRAM) capable of canceling out complementary noise developed in plate electrodes of memory cell capacitors
12/31/2002US6501323 Voltage switching circuit
12/27/2002WO2002029817A3 Upscaled clock feeds memory to make parallel waves
12/26/2002US20020196690 Semiconductor memory device
12/26/2002US20020196674 Semiconductor memory device
12/26/2002US20020196669 Decoding scheme for a stacked bank architecture
12/26/2002US20020196667 Read circuit of nonvolatile semiconductor memory
12/26/2002US20020196659 Non-Volatile memory
12/26/2002US20020196058 Low-amplitude driver circuit
12/26/2002US20020196053 Semiconductor integrated circuit and semiconductor logic circuit used in the integrated circuit
12/25/2002CN1097233C Word line driving circuit for semiconductor memory device
12/24/2002US6498765 Semiconductor integrated circuit
12/24/2002US6498759 System for automatic generation of suitable voltage source on motherboard
12/24/2002US6498758 Twisted bitlines to reduce coupling effects (dual port memories)
12/24/2002US6498755 Semiconductor storage device conducting a late-write operation and controlling a test read-operation to read data not from a data latch circuit but from a memory core circuit regardless of whether a preceding address and a present address match each other
12/24/2002US6498754 Memory array organization for static arrays
12/24/2002US6498750 Boot block flash memory control circuit; IC memory card and semiconductor memory device incorporating the same; and erasure method for boot block flash memory
12/24/2002US6498741 Semiconductor memory device
12/24/2002US6498065 Memory address decode array with vertical transistors
12/19/2002WO2002101928A1 Nonvolatile selector, and integrated circuit device
12/19/2002WO2002080227A3 Memory address and decode circuits with ultra thin body transistors
12/19/2002WO2001075896A9 Flash with consistent latency for read operations
12/19/2002US20020194443 Memory circuitry with auxiliary word line to obtain predictable array output when an invalid address is requested
12/19/2002US20020192895 Fabrication techniques for addressing cross-point diode memory arrays
12/19/2002US20020191603 Method and system for dynamic segmentation of communications packets
12/19/2002US20020191478 Semiconductor memory with wordline timing
12/19/2002US20020191475 Communications architecture for memory-based devices
12/19/2002US20020191473 Semiconductor memory device and method of selecting word line thereof
12/19/2002US20020191470 Architecture, method(s) and circuitry for low power memories
12/19/2002US20020191457 Memory architecture with single-port cell and dual-port (read and write) functionality)
12/19/2002US20020191447 Semiconductor integrated circuit
12/19/2002US20020191446 Semiconductor memory device having self-timing circuit
12/19/2002US20020191442 Non-volatile semiconductor memory device and semiconductor disk device
12/19/2002US20020191434 Addressing and sensing a cross-point diode memory array
12/19/2002US20020190708 Memory device tester and method for testing reduced power states
12/19/2002DE10127194A1 Control method for logic address mapping uses virtual memory addressing for masking out non-serviceable memory cells
12/18/2002EP1267355A1 One-shot signal generating circuit
12/18/2002EP1266382A1 Trimming method and system for wordline booster to minimize process variation of boosted wordline voltage
12/18/2002EP0853806B1 Integrated circuit for storage and retrieval of multiple digital bits per nonvolatile memory cell
12/18/2002CN1385905A Magnetic RAM of transistor with vertical structure and making method thereof
12/17/2002US6496916 System for flexible memory paging in partitioning memory
12/17/2002US6496889 Chip-to-chip communication system using an ac-coupled bus and devices employed in same
12/17/2002US6496445 Semiconductor memory device having altered clock frequency for address and/or command signals, and memory module and system having the same
12/17/2002US6496444 Elimination of precharge operation in synchronous flash memory
12/17/2002US6496442 Dynamic random access memory device and semiconductor integrated circuit device
12/17/2002US6496441 Semiconductor memory device with improved data propagation characteristics of a data bus
12/17/2002US6496440 Method and system for accessing rows in multiple memory banks within an integrated circuit
12/17/2002US6496432 Method and apparatus for testing a write function of a dual-port static memory cell
12/17/2002US6496409 Variable capacity semiconductor memory device
12/17/2002US6496400 Memory architecture and addressing for optimized density in integrated circuit package or on circuit board
12/12/2002WO2002099809A2 Method and device for masking out non-serviceable memory cells
12/12/2002US20020188893 Series connected TC unit type ferroelectric RAM and test method thereof
12/12/2002US20020186611 Semiconductor memory device having hierarchical word line structure
12/12/2002US20020186610 Integrated memory having a memory cell array with a plurality of segments and method for operating the integrated memory
12/12/2002US20020186609 Semiconductor memory device with reduced power consumption during refresh operation
12/12/2002US20020186590 Nonvolatile semiconductor memory device having hierarchical sector structure
12/12/2002US20020185337 Semiconductor device with non-volatile memory and random access memory
12/12/2002DE10159368A1 Halbleiterspeichervorrichtung mit verringertem Leistungsverbrauch während der Auffrischoperation A semiconductor memory device with reduced power consumption during the refresh operation
12/12/2002DE10119125C1 Verfahren zum Vergleich der Adresse eines Speicherzugriffs mit einer bereits bekannten Adresse einer fehlerhaften Speicherzelle A method for comparing the address of a memory access to a known address of a defective memory cell
12/11/2002EP1265287A2 Non-volatile memory
12/11/2002EP1265286A2 Integrated circuit structure
12/11/2002EP1265253A2 Cross-Point diode memory arrays
12/11/2002EP1265248A2 Addressing a cross-point diode memory array
12/11/2002CN1096080C Semiconductor memory device having dual word line configuration
12/10/2002USRE37930 DRAM including an address space divided into individual blocks having memory cells activated by row address signals
12/10/2002US6493284 Semiconductor memory device having hierarchical wordline structure
12/10/2002US6493283 Architecture, method (s) and circuitry for low power memories
12/10/2002US6493276 Word line boost circuit
12/10/2002US6493259 Pulse write techniques for magneto-resistive memories
12/05/2002US20020184468 High speed address sequencer
12/05/2002US20020184456 Interleaver memory access apparatus and method of mobile communication system
12/05/2002US20020184437 Memory architecture for supporting concurrent access of different types
12/05/2002US20020181315 Nonvolatile semiconductor memory device having selective multiple-speed operation mode
12/05/2002US20020181301 Semiconductor storage and method for testing the same
12/05/2002US20020181284 Nonvolatile memory and method of driving the same
12/05/2002US20020179943 Semiconductor integrated circuit device
12/05/2002DE10126567A1 Integrated circuit used in memory circuits in silicon technology
12/05/2002DE10121837C1 Speicherschaltung mit mehreren Speicherbereichen A memory circuit comprising a plurality of memory areas
12/04/2002EP1262991A2 Multi-port random access memory
12/04/2002EP1262990A1 Memory architecture for supporting concurrent access of different types
12/04/2002EP1183690B1 Memory array with address scrambling
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