Patents
Patents for G11C 8 - Arrangements for selecting an address in a digital store (19,368)
02/2003
02/06/2003US20030026506 System for generating a read only memory image
02/06/2003US20030026161 Semiconductor memory
02/06/2003US20030026156 Semiconductor device
02/06/2003US20030026140 Semiconductor memory having multiple redundant columns with offset segmentation boundaries
02/06/2003US20030026138 Semiconductor memory device having write latency operation and method thereof
02/06/2003US20030026120 Current sensing method and apparatus particularly useful for a memory array of cells having diode-like characteristics
02/06/2003US20030025531 Method and apparatus for low power domino decoding
02/05/2003EP1282315A2 Smartcard for use with a receiver of encrypted broadcast signals, and receiver
02/05/2003EP1119858B1 Decoder element for producing an output signal with three different potentials and operating method for said decoder element
02/05/2003CN1395256A 移位寄存器及电子装置 Shift registers and electronic devices
02/05/2003CN1101048C Bit map addressing schemes for fast memory
02/04/2003US6516392 Address and data transfer circuit
02/04/2003US6515933 Semiconductor device and semiconductor storage device testing method
02/04/2003US6515932 Memory circuit
02/04/2003US6515924 Semiconductor memory device
02/04/2003US6515911 Circuit structure for providing a hierarchical decoding in semiconductor memory devices
02/04/2003US6515904 Method and system for increasing programming bandwidth in a non-volatile memory device
02/04/2003US6515885 Tri-stating address input circuit
01/2003
01/30/2003US20030023909 Interleave address generator
01/30/2003US20030023805 Memory module and system, an information processing apparatus and a mehtod of use
01/30/2003US20030022420 Three-dimensional memory array incorporating serial chain diode stack
01/30/2003US20030021176 Programmable address logic for solid state diode-based memory
01/30/2003US20030021170 Integrated dynamic memory and operating method
01/30/2003US20030021152 Voltage boost circuit using supply voltage detection to compensate for supply voltage variations in read mode voltages
01/30/2003US20030021148 Current sensing method and apparatus particularly useful for a memory array of cells having diode-like characteristics
01/30/2003US20030021147 Optically programmable address logic for solid state diode-based memory
01/30/2003US20030020684 Device comprising an array of pixels
01/28/2003US6513081 Memory device which receives an external reference voltage signal
01/28/2003US6512716 Memory device with support for unaligned access
01/28/2003US6512710 Reliability test method and circuit for non-volatile memory
01/28/2003US6512705 Method and apparatus for standby power reduction in semiconductor devices
01/28/2003US6512693 Semiconductor device that enables simultaneous read and write/erase operation
01/28/2003US6512257 System with meshed power and signal buses on cell array
01/23/2003WO2003007306A2 Method and system for banking register file memory arrays
01/23/2003WO2003007303A2 Memory device having different burst order addressing for read and write operations
01/23/2003WO2002049035A3 Memory device and method for the operation of the same
01/23/2003WO2002015193A3 Burst read word line boosting
01/23/2003WO2001091296A3 Block ram having multiple configurable write modes for use in a field programmable gate array
01/23/2003US20030018845 Memory device having different burst order addressing for read and write operations
01/23/2003US20030016573 Non-volatile semiconductor memory device and information apparatus
01/23/2003US20030016564 Semiconductor memory with precharge control
01/23/2003US20030016068 Circuit arrangement and method for discharging at least one circuit node
01/23/2003US20030016063 Internal clock generating circuit of semiconductor memory device and method thereof
01/22/2003EP1278198A2 Semiconductor memory device
01/22/2003CN1392568A Word line driver of semiconductor memory device
01/22/2003CN1392564A 非易失性存储器 Non-volatile memory
01/21/2003US6510102 Method for generating memory addresses for accessing memory-cell arrays in memory devices
01/21/2003US6510101 Clock-synchronous semiconductor memory device
01/21/2003US6510100 Synchronous memory modules and memory systems with selectable clock termination
01/21/2003US6510098 Method and apparatus for transferring data in a dual port memory
01/21/2003US6510097 DRAM interface circuit providing continuous access across row boundaries
01/21/2003US6510086 Nonvolatile semiconductor memory
01/21/2003US6510075 Memory cell with increased capacitance
01/21/2003US6510072 Nonvolatile ferroelectric memory device and method for detecting weak cell using the same
01/21/2003US6509774 Delay circuit using current source
01/21/2003US6509756 Method and apparatus for low capacitance, high output impedance driver
01/21/2003US6509595 DRAM cell fabricated using a modified logic process and method for operating same
01/16/2003US20030014689 Flash EEprom system
01/16/2003US20030012075 Semiconductor memory device
01/16/2003US20030012074 Semiconductor memory with improved soft error resistance
01/16/2003US20030012072 Method and system for banking register file memory arrays
01/16/2003US20030012059 Semiconductor integrated circuit device having spare word lines
01/16/2003US20030012057 Acquisition process by analog signal sampling, and an acquisition system to implement such a process
01/16/2003US20030012052 Non-volatile semiconductor memory device for selectively re-checking word lines
01/16/2003US20030011313 Power supply control circuit for use in semiconductor storage device
01/15/2003CN1391228A Semiconductor memory for power consumption on reducing update time
01/15/2003CN1391166A Semiconductor memory devices
01/14/2003US6507885 Memory system, method and predecoding circuit operable in different modes for selectively accessing multiple blocks of memory cells for simultaneous writing or erasure
01/14/2003US6507534 Column decoder circuit for page reading of a semiconductor memory
01/14/2003US6507533 Semiconductor memory device having a word line activation block
01/14/2003US6507532 Semiconductor memory device having row-related circuit operating at high speed
01/14/2003US6507531 Cache column multiplexing using redundant form addresses
01/14/2003US6507514 Integrated circuit memory chip for use in single or multi-chip packaging
01/14/2003US6507508 Pattern layout of transfer transistors employed in row decoder
01/09/2003WO2002080178A3 System and method for achieving fast switching of analog voltages on a large capacitive load
01/09/2003US20030009720 Address information detecting apparatus and address information detecting method
01/09/2003US20030007387 CG-WL voltage boosting scheme for twin MONOS
01/09/2003US20030007384 Nonvolatile semiconductor memory device
01/09/2003US20030007382 Semiconductor memory device
01/09/2003US20030006802 Decoder circuit
01/09/2003US20030006446 Memory address and decode circuits with ultra thin body transistors
01/09/2003US20030006283 Information storage apparatus and information processing apparatus using the same
01/08/2003EP1274096A2 Control gate and word line voltage boosting scheme for twin MONOS memory cells
01/08/2003EP1274094A2 Bit line decoding scheme and circuit for dual bit memory with a dual bit selection
01/08/2003EP1274090A1 Non-volatile semiconductor memory device and information apparatus
01/08/2003EP0829095B1 Method and apparatus for reducing latency time on an interface by overlapping transmitted packets
01/08/2003CN1389919A Cross-point diode storage array addressing mfg. technology
01/08/2003CN1098162C Ink jet print head identification circuit with serial out, dynamic shift registers
01/07/2003US6504788 Semiconductor memory with improved soft error resistance
01/07/2003US6504787 Semiconductor memory device with reduced power consumption during refresh operation
01/07/2003US6504783 Semiconductor device having early operation high voltage generator and high voltage supplying method therefor
01/07/2003US6504758 Control circuit for a variable-voltage regulator of a nonvolatile memory with hierarchical row decoding
01/07/2003US6504753 Method and apparatus for discharging memory array lines
01/07/2003US6504745 High performance erasable programmable read-only memory (EPROM) devices with multiple dimension first-level bit lines
01/07/2003US6504742 3-D memory device for large storage capacity
01/02/2003US20030005208 Synchronous integrated circuit device
01/02/2003US20030002615 Shift register and electronic apparatus
01/02/2003US20030002383 Address transition detecting circuit
01/02/2003US20030002381 Semiconductor memory for logic-hybrid memory
01/02/2003US20030002380 Decoder circuit in a semiconductor memory device