Patents
Sitemap › H01 - Basic electric elements › H01L - Semiconductor devices; Electric solid state devices not otherwise provided for › H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
Patents for H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof (658,974)
12/1998
12/22/1998US5852490 Projection exposure method and apparatus
12/22/1998US5852488 Electro-optical device and method of driving the same
12/22/1998US5852481 Liquid crystal display with two gate electrodes each having a non-anodizing and one anodizing metallic layer and method of fabricating
12/22/1998US5852366 High voltage level shift circuit including CMOS transistor having thin gate insulating film
12/22/1998US5852328 Semiconductor device and method of manufacturing the same
12/22/1998US5852327 Semiconductor device
12/22/1998US5852326 Face-up semiconductor chip assembly
12/22/1998US5852324 Plastic body surface-mounting semiconductor power device having dimensional characteristics optimized for use of standard shipping and testing modes
12/22/1998US5852319 Gate electrode for semiconductor device
12/22/1998US5852317 Method to reduce gate oxide damage due to non-uniform plasmas in read only memory arrays
12/22/1998US5852316 Complementary heterojunction amplifier
12/22/1998US5852315 N-sided polygonal cell layout for multiple cell transistor
12/22/1998US5852314 Thin epitaxy resurf integrated circuit containing high voltage p-channel and n-channel devices with source or drain not tied to ground
12/22/1998US5852312 Flash eeprom cell
12/22/1998US5852311 Non-volatile memory devices including capping layer contact holes
12/22/1998US5852310 Multi-level transistor fabrication method with a patterned upper transistor substrate and interconnection thereto
12/22/1998US5852307 Semiconductor device with capacitor
12/22/1998US5852300 Device for sensing a flat zone of a wafer for use in a wafer probe tester
12/22/1998US5851929 Controlling semiconductor structural warpage in rapid thermal processing by selective and dynamic control of a heating source
12/22/1998US5851928 Method of etching a semiconductor substrate
12/22/1998US5851927 Method of forming a semiconductor device by DUV resist patterning
12/22/1998US5851926 Method for etching transistor gates using a hardmask
12/22/1998US5851924 Method for fabricating semiconductor wafers
12/22/1998US5851923 Integrated circuit and method for forming and integrated circuit
12/22/1998US5851922 Process for fabricating a device using nitrogen implantation into silicide layer
12/22/1998US5851921 Semiconductor device and method for forming the device using a dual layer, self-aligned silicide to enhance contact performance
12/22/1998US5851920 Method of fabrication of metallization system
12/22/1998US5851919 Method for forming interconnections in an integrated circuit
12/22/1998US5851918 Methods of fabricating liquid crystal display elements and interconnects therefor
12/22/1998US5851917 Method for manufacturing a multi-layer wiring structure of a semiconductor device
12/22/1998US5851916 Formation of a self-aligned integrated circuit structures using planarization to form a top surface
12/22/1998US5851915 Method of manufacturing a semiconductor device through a reduced number of simple processes at a relatively low cost
12/22/1998US5851914 Method of fabricating a metal contact structure
12/22/1998US5851913 Method for forming a multilevel interconnect structure of an integrated circuit by a single via etch and single fill process
12/22/1998US5851912 Modified tungsten-plug contact process
12/22/1998US5851911 Mask repattern process
12/22/1998US5851910 Method of fabricating a bonding pad window
12/22/1998US5851909 Method of producing semiconductor device using an adsorption layer
12/22/1998US5851908 Method for introduction of an impurity dopant in SiC, a semiconductor device formed by the method and a use of highly doped amorphous layer as a source for dopant diffusion into SiC
12/22/1998US5851906 Impurity doping method
12/22/1998US5851904 Method of manufacturing microcrystalline layers and their utilization
12/22/1998US5851903 Method of forming closely pitched polysilicon fuses
12/22/1998US5851902 Semiconductor layer structure and recording medium for a large capacity memory
12/22/1998US5851901 Method of manufacturing an isolation region of a semiconductor device with advanced planarization
12/22/1998US5851900 Method of manufacturing a shallow trench isolation for a semiconductor device
12/22/1998US5851899 Gapfill and planarization process for shallow trench isolation
12/22/1998US5851898 Method of forming stacked capacitor having corrugated side-wall structure
12/22/1998US5851897 Method of forming a dram cell with a crown-fin-pillar structure capacitor
12/22/1998US5851896 Conductive exotic-nitride barrier layer for high-dielectric-constant material electrodes
12/22/1998US5851894 Method of vertically integrating microelectronic systems
12/22/1998US5851893 Method of making transistor having a gate dielectric which is substantially resistant to drain-side hot carrier injection
12/22/1998US5851892 Fabrication sequence employing an oxide formed with minimized inducted charge and/or maximized breakdown voltage
12/22/1998US5851891 IGFET method of forming with silicide contact on ultra-thin gate
12/22/1998US5851890 Process for forming integrated circuit structure with metal silicide contacts using notched sidewall spacer on gate electrode
12/22/1998US5851889 Semiconductor gate conductor with a substantially uniform doping profile having minimal susceptibility to dopant penetration into the underlying gate dielectric
12/22/1998US5851888 Controlled oxide growth and highly selective etchback technique for forming ultra-thin oxide
12/22/1998US5851887 Deep sub-micron polysilicon gap formation
12/22/1998US5851886 Method of large angle tilt implant of channel region
12/22/1998US5851885 Manufacturing method for ROM components having a silicon controlled rectifier structure
12/22/1998US5851884 Structure and manufacturing method for ROM
12/22/1998US5851883 High density integrated circuit process
12/22/1998US5851882 ZPROM manufacture and design and methods for forming thin structures using spacers as an etching mask
12/22/1998US5851881 Method of making monos flash memory for multi-level logic
12/22/1998US5851880 Method of making nonvolatile memory elements with selector transistors
12/22/1998US5851879 Method for fabricating compact contactless trenched flash memory cell
12/22/1998US5851878 Method of forming a rugged polysilicon fin structure in DRAM
12/22/1998US5851877 Method of forming a crown shape capacitor
12/22/1998US5851876 Method of manufacturing dynamic random access memory
12/22/1998US5851875 Process for forming capacitor array structure for semiconductor devices
12/22/1998US5851874 Method of planarizing memory cells
12/22/1998US5851873 Method of making semiconductor memory device
12/22/1998US5851872 Method of fabricating dynamic random access memory
12/22/1998US5851871 Process for manufacturing integrated capacitors in MOS technology
12/22/1998US5851870 Method for making a capacitor
12/22/1998US5851869 Manufacture of semiconductor device having low contact resistance
12/22/1998US5851868 Methods of forming integrated decoupling capacitors
12/22/1998US5851867 Rugged stacked oxide layer structure and method of fabricating same
12/22/1998US5851866 Fabrication method for CMOS with sidewalls
12/22/1998US5851865 Method of manufacturing semiconductor device having mask layer forming step for ion implantation
12/22/1998US5851864 Method of fabricating BiCMOS devices
12/22/1998US5851863 Semiconductor device
12/22/1998US5851862 Method of crystallizing a silicon film
12/22/1998US5851861 MIS semiconductor device having an LDD structure and a manufacturing method therefor
12/22/1998US5851860 Semiconductor device and method for producing the same
12/22/1998US5851859 Method for manfacturing a thin film transistor by using temperature difference
12/22/1998US5851858 Method for producing a multiplicity of microelectronic circuits on SOI
12/22/1998US5851856 Manufacture of application-specific IC
12/22/1998US5851855 Process for manufacturing a MOS-technology power device chip and package assembly
12/22/1998US5851853 Method of attaching a die onto a pad of a lead frame
12/22/1998US5851852 Die attached process for SiC
12/22/1998US5851848 Method and apparatus for aligning the position of die on a wafer table
12/22/1998US5851847 Photonic device and process for fabricating the same
12/22/1998US5851846 Polishing method for SOI
12/22/1998US5851845 Process for packaging a semiconductor die using dicing and testing
12/22/1998US5851844 Ferroelectric semiconductor device and method of manufacture
12/22/1998US5851843 Method of manufacturing a super conduction field effect transistor
12/22/1998US5851842 Measurement system and measurement method
12/22/1998US5851841 Method for producing ferroelectric film element, and ferroelectric film element and ferroelectric memory element produced by the method
12/22/1998US5851834 Methods for determining impurity distributions in microelectronic structures formed from aluminum-containing materials
12/22/1998US5851738 Method comprising substrates coated with an antihalation layer that contains a resin binder comprising anthracene units
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