Patents
Sitemap › H01 - Basic electric elements › H01L - Semiconductor devices; Electric solid state devices not otherwise provided for › H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
Patents for H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof (658,974)
09/1999
09/28/1999US5960297 Shallow trench isolation structure and method of forming the same
09/28/1999US5960296 Method for aligning the device layers in a semiconductor device
09/28/1999US5960295 Method for fabricating a storage plate of a semiconductor capacitor
09/28/1999US5960294 Method of fabricating a semiconductor device utilizing polysilicon grains
09/28/1999US5960293 Methods including oxide masks for fabricating capacitor structures for integrated circuit devices
09/28/1999US5960291 Asymmetric channel transistor and method for making same
09/28/1999US5960289 Method for making a dual-thickness gate oxide layer using a nitride/oxide composite region
09/28/1999US5960287 Method for manufacturing semiconductor memory devices having a ROM device
09/28/1999US5960286 Method of manufacturing power semiconductor devices
09/28/1999US5960285 Flash EEPROM device
09/28/1999US5960284 Method for forming vertical channel flash memory cell and device manufactured thereby
09/28/1999US5960283 Nonvolatile semiconductor memory device and method of fabrication of the same
09/28/1999US5960282 Method for fabricating a dynamic random access memory with a vertical pass transistor
09/28/1999US5960281 Methods of fabricating microelectronic electrode structures using hemispherical grained (HSG) silicon
09/28/1999US5960280 Method of fabricating a fin/cavity capacitor structure for DRAM cell
09/28/1999US5960279 Method of fabricating a capacitor on a rugged stacked oxide layer
09/28/1999US5960278 Method of manufacturing SRAM cell
09/28/1999US5960277 Method of making a merged device with aligned trench FET and buried emitter patterns
09/28/1999US5960276 Using an extra boron implant to improve the NMOS reverse narrow width effect in shallow trench isolation process
09/28/1999US5960275 Power MOSFET fabrication process to achieve enhanced ruggedness, cost savings, and product reliability
09/28/1999US5960274 Oxide formation process for manufacturing programmable logic device
09/28/1999US5960273 Method of manufacturing a semiconductor device including a bipolar transistor
09/28/1999US5960272 Element-isolating construct of a semiconductor integrated circuit having an offset region between impurity doped regions, and process of manufacturing the construct
09/28/1999US5960271 Short channel self-aligned VMOS field effect transistor
09/28/1999US5960270 Method for forming an MOS transistor having a metallic gate electrode that is formed after the formation of self-aligned source and drain regions
09/28/1999US5960269 Method for manufacturing a field effect transistor using an auxiliary layer deposited at a very flat incident angle
09/28/1999US5960268 Semiconductor device and method of fabricating the same
09/28/1999US5960265 Method of making EEPROM having coplanar on-insulator FET and control gate
09/28/1999US5960264 Method of manufacturing an insulated gate semiconductor device
09/28/1999US5960263 Laser programming of CMOS semiconductor devices using make-link structure
09/28/1999US5960262 Stitch bond enhancement for hard-to-bond materials
09/28/1999US5960261 Method for manufacturing semiconductor package
09/28/1999US5960260 Semiconductor device, its manufacturing method, and dicing adhesive element therefor
09/28/1999US5960257 Method distributed feedback semiconductor laser for fabricating
09/28/1999US5960256 Wafer layout of semiconductor device and manufacturing method thereof
09/28/1999US5960255 Calibration standard for 2-D and 3-D profilometry in the sub-nanometer range and method of producing it
09/28/1999US5960254 Methods for the preparation of a semiconductor structure having multiple levels of self-aligned interconnection metallization
09/28/1999US5960253 Method of manufacturing semiconductor memory device capable of readily repairing defective portion resulting from mask defect
09/28/1999US5960252 Method for manufacturing a semiconductor memory device having a ferroelectric capacitor
09/28/1999US5960225 Substrate treatment apparatus
09/28/1999US5960159 Heat treatment of semiconductor wafers where upper heater directly heats upper wafer in its entirety and lower heater directly heats lower wafer in its entirety
09/28/1999US5960106 Sample inspection apparatus and sample inspection method
09/28/1999US5960014 Thin film resistor for optoelectronic integrated circuits
09/28/1999US5960008 Test circuit
09/28/1999US5959922 Ferroelectric random access memory device with reference cell array blocks
09/28/1999US5959908 Semiconductor memory device having spare word lines
09/28/1999US5959895 Nonvolatile semiconductor memory cell capable of saving overwritten cell and its saving method
09/28/1999US5959888 Non-volatile semiconductor memory device and method of manufacturing non-volatile semiconductor memory device
09/28/1999US5959887 Electrically erasable programmable nonvolatile semiconductor memory having dual operation function
09/28/1999US5959879 Ferroelectric memory devices having well region word lines and methods of operating same
09/28/1999US5959878 Ferroelectric memory cell with shunted ferroelectric capacitor and method of making same
09/28/1999US5959877 Mask ROM
09/28/1999US5959854 Voltage step-up circuit and method for controlling the same
09/28/1999US5959784 Optical projection systems and projection-exposure apparatus comprising same
09/28/1999US5959779 Laser irradiation apparatus
09/28/1999US5959721 Projection exposure apparatus and projection exposure method
09/28/1999US5959515 High Q integrated resonator structure
09/28/1999US5959484 Feed back circuit
09/28/1999US5959471 Method and apparatus for reducing the bias current in a reference voltage circuit
09/28/1999US5959427 Method and apparatus for compensating for reaction forces in a stage assembly
09/28/1999US5959409 Ceramic protection for heated metal surfaces of plasma processing chamber exposed to chemically aggressive gaseous environment therein and method protecting such heated metal surfaces
09/28/1999US5959396 High current nova dual slit electrode enchancement
09/28/1999US5959363 Semiconductor device with improved encapsulating resin
09/28/1999US5959362 Device mounting a semiconductor element on a wiring substrate including an adhesive material having first and second adhesive components with different cure characteristics
09/28/1999US5959361 Dielectric pattern
09/28/1999US5959359 Semiconductor device with a copper wiring pattern
09/28/1999US5959358 Oxidation resistant high conductivity copper layers for microelectronic applications and process of making same
09/28/1999US5959357 Fet array for operation at different power levels
09/28/1999US5959354 Connection components with rows of lead bond sections
09/28/1999US5959353 Semiconductor device
09/28/1999US5959349 Transfer molding encapsulation of a semiconductor die with attached heat sink
09/28/1999US5959348 Construction of PBGA substrate for flip chip packing
09/28/1999US5959346 Method for fabricating metal bumps onto electronic device
09/28/1999US5959340 Thermoplastic mounting of a semiconductor die to a substrate having a mismatched coefficient of thermal expansion
09/28/1999US5959337 Air gap spacer formation for high performance MOSFETs
09/28/1999US5959335 Device design for enhanced avalanche SOI CMOS
09/28/1999US5959334 Semiconductor memory device
09/28/1999US5959333 Reduction of dopant diffusion by the co-implantation of impurities into the transistor gate conductor
09/28/1999US5959332 Electrostatic-discharge protection device and method for making the same
09/28/1999US5959331 High density transistor component and its manufacturing method
09/28/1999US5959330 Semiconductor device and method of manufacturing same
09/28/1999US5959329 Insulating oxide film formed by high-temperature wet oxidation
09/28/1999US5959328 Electrically programmable memory cell arrangement and method for its manufacture
09/28/1999US5959327 Capacitor compatible with high dielectric constant materials having a low contact resistance layer and the method for forming same
09/28/1999US5959326 Capacitor incorporated in semiconductor device having a lower electrode composed of multi-layers or of graded impurity concentration
09/28/1999US5959325 Method for forming cornered images on a substrate and photomask formed thereby
09/28/1999US5959324 Semiconductor device including an improved terminal structure
09/28/1999US5959322 Isolated SOI memory structure with vertically formed transistor and storage capacitor in a substrate
09/28/1999US5959321 DRAM matrix of basic organizational units each with pair of capacitors with hexagon shaped planar portion
09/28/1999US5959320 Semiconductor die having on-die de-coupling capacitance
09/28/1999US5959319 Semiconductor memory device having word line conductors provided at lower level than memory cell capacitor and method of manufacturing same
09/28/1999US5959318 Solid state image pickup device with polygates
09/28/1999US5959317 High frequency hetero junction type field effect transistor using multilayer electron feed layer
09/28/1999US5959314 Polycrystalline silicon from the crystallization of microcrystalline silicon
09/28/1999US5959313 Thin film semiconductor having a monocrystalline region containing carbon, nitrogen and oxygen and crystallization promotor metal component
09/28/1999US5959308 Epitaxial layer on a heterointerface
09/28/1999US5959305 Method and apparatus for monitoring charge neutralization operation
09/28/1999US5959304 Semiconductor exposure apparatus
09/28/1999US5959157 Process for making hydroxy-substituted ethynylated biphenyl compounds
09/28/1999US5959068 Adhesive tape for electronic parts and liquid adhesive
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