Patents
Patents for H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof (658,974)
01/2000
01/25/2000US6017824 Forming silicon oxide layer on fuse structures on integrated circuits; forming polysilicon shape on top surface of silicon oxide; forming via holes in dielectric layers; exposing portion of top surface of polysilicon shape; forming spacers
01/25/2000US6017823 Method of forming a MOS field effect transistor with improved gate side wall insulation films
01/25/2000US6017822 Method of thinning semiconductor wafer of smaller diameter than thinning equipment was designed for
01/25/2000US6017821 Chemical-mechanical polishing method for forming plugs
01/25/2000US6017820 Integrated vacuum and plating cluster system
01/25/2000US6017819 Method for forming a polysilicon/amorphous silicon composite gate electrode
01/25/2000US6017818 Process for fabricating conformal Ti-Si-N and Ti-B-N based barrier films with low defect density
01/25/2000US6017817 Method of fabricating dual damascene
01/25/2000US6017816 Forming electrical elements on field oxide regions of semiconductor silicon wafer; forming barrier layer; forming metal layer and anti-reflection layer; photoresist patterning; etching to form interconnect lines; stripping pattern
01/25/2000US6017815 Method of fabricating a border-less via
01/25/2000US6017814 Structure and fabrication method for stackable, air-gap-containing low epsilon dielectric layers
01/25/2000US6017813 Method for fabricating a damascene landing pad
01/25/2000US6017812 Bump bonding method and bump bonding apparatus
01/25/2000US6017810 Process for fabricating field effect transistor with a self-aligned gate to device isolation
01/25/2000US6017809 Method of manufacturing semiconductor device
01/25/2000US6017808 Depositing polysilicon onto gate oxide followed by nitrogen doping and annealing, removing polysilicon from top of polysilicon layer to provide secon polysilicon layer
01/25/2000US6017807 Forming p-type gallium nitride layer which is doped with p-type dopants; thermally annealing while supplying flow of inert gas
01/25/2000US6017806 Immersing partially fabricated semiconductor in deuterium ambient; heating to cause dissociation of hydrogen and deuterium at interface while excess deuterium remains in structure; lowering temperature and completing fabrication
01/25/2000US6017805 Moving contaminants to region near surface of said semiconductor film by depositing charge on surface, charge being opposite to charge of contaminants; removing chargedregion to reduce concentration of contaminants on film
01/25/2000US6017804 Method and apparatus for cleaving semiconductor material
01/25/2000US6017803 Method to prevent dishing in chemical mechanical polishing
01/25/2000US6017802 Ultra-short transistor fabrication scheme for enhanced reliability
01/25/2000US6017801 Method for fabricating field effect transistor
01/25/2000US6017800 Semiconductor device and method of fabricating thereof
01/25/2000US6017799 Method of fabricating dynamic random memory
01/25/2000US6017798 FET with stable threshold voltage and method of manufacturing the same
01/25/2000US6017797 Method of fabricating a semiconductor device including complementary MOSFET and power MOSFET
01/25/2000US6017796 Method of fabricating flash electrically-erasable and programmable read-only memory (EEPROM) device
01/25/2000US6017795 Method of fabricating buried source to shrink cell dimension and increase coupling ratio in split-gate flash
01/25/2000US6017794 Depositing and patterning lower metallization layer of chromium and dielectric layer; depositing chromium caps over source and drain regions; patterning and etching trenches; filling trenches with dielectric layer; depositing metal
01/25/2000US6017793 Method of forming a memory cell of a nonvolatile semiconductor memory device
01/25/2000US6017792 Process for fabricating a semiconductor device including a nonvolatile memory cell
01/25/2000US6017791 Depositing silicon nitride layer over substrate; forming second silicon nitride layer over first layer; thermally annealing in oxidative atmosphere to form silicon nitride/silicon oxide layer
01/25/2000US6017790 Forming dielectric layer over substrate having memory circuit and logic circuit regions; patterning, forming conductive layer and refractory metal oxide layer and masking; hydrogen treating; removing mask and repeating
01/25/2000US6017789 Method of forming a Ta2 O5 dielectric layer with amorphous diffusion barrier layer and method of forming a capacitor having a b. Ta.su2 O5 dielectric layer with amorphous diffusion barrier layer
01/25/2000US6017788 Sequentially forming oxide layer and borophosphosilicateglass layer over semiconductor substrate having drain/source regions; using photolithography and etching to form contact window; forming titanium silicide and titanium nitride layers
01/25/2000US6017787 Integrated circuit with twin tub
01/25/2000US6017786 Method for forming a low barrier height oxide layer on a silicon substrate
01/25/2000US6017785 Method for improving latch-up immunity and interwell isolation in a semiconductor device
01/25/2000US6017784 Manufacture method of semiconductor device with suppressed impurity diffusion from gate electrode
01/25/2000US6017783 Method of manufacturing a semiconductor device using an insulated gate electrode as a mask
01/25/2000US6017782 Thin film transistor and method of forming thin film transistors
01/25/2000US6017781 Forming gate dielectric film to cover gate electrode on dielectric film; forming polysilicon film; doping silicon or nitrogen into polysilicon film; heat treating to convert amorphous silicon into polysilicon
01/25/2000US6017780 Passivation scheme for LCD and other applications
01/25/2000US6017779 Fabrication method for a thin film semiconductor device, the thin film semiconductor device itself, liquid crystal display, and electronic device
01/25/2000US6017778 Method for making power integrated circuit
01/25/2000US6017777 Method of forming a plating layer of a lead frame
01/25/2000US6017776 Method of attaching a leadframe to singulated semiconductor dice
01/25/2000US6017775 Process for manufacturing a sensor with a metal electrode in a metal oxide semiconductor (MOS) structure
01/25/2000US6017774 Method for producing group III-V compound semiconductor and fabricating light emitting device using such semiconductor
01/25/2000US6017773 Stabilizing process for porous silicon and resulting light emitting device
01/25/2000US6017771 Method and system for yield loss analysis by yield management system
01/25/2000US6017696 Controlling nucleic acid hybridization by connecting multiple electrical sources to several location where a plurality of nucleic acids with target nucleic acids are attached, apply a negative potential, removing non specific nucleic acid
01/25/2000US6017678 Photocurable elastomeric mixture and recording material obtained therefrom for the production of relief printing plates
01/25/2000US6017676 Photoresist composition comprising a copolymer resin
01/25/2000US6017675 Polymerization catalyst
01/25/2000US6017663 Coating, exposing, developing and heat treating photoresist in air conditioned/chemically filtered environment whereby photolithography is temporarily stopped for filter change in response to detected high concentration of alkaline material
01/25/2000US6017659 Forming phase shifting photomask with minimal masking steps where the phase shifter comprises a transparent mask substrate and stepped, self-aligned phase transition portion
01/25/2000US6017634 Carboxyl-containing polyunsaturated fluxing agent and carboxyl-reactive neutralizing agent as adhesive
01/25/2000US6017614 Plasma-enhanced chemical vapor deposited SIO2 /SI3 N4 multilayer passivation layer for semiconductor applications
01/25/2000US6017585 For use in the application of a viscous precursor fluid on a substrate surface of a silicon substrate
01/25/2000US6017463 Forming a slurry including abrasive particles having a solubility coating, in an aqueous concentrate having specific particle size, blended with suspension agent, mixed with deizonized water; mixing with oxidzer; supplying to the pad
01/25/2000US6017438 Method for producing circuit substrate having bump contact point and jet stream type plating apparatus used therefor
01/25/2000US6017437 Process chamber and method for depositing and/or removing material on a substrate
01/25/2000US6017424 Laser assisted surface reformation method of high polymer material
01/25/2000US6017401 Conductivity improvement in thin films of refractory metal
01/25/2000US6017397 Automated washing method
01/25/2000US6017396 Plasma film forming apparatus that prevents substantial irradiation damage to the substrate
01/25/2000US6017395 Gas pressure regulation in vapor deposition
01/25/2000US6017221 Process depending on plasma discharges sustained by inductive coupling
01/25/2000US6017144 Method and apparatus for depositing highly oriented and reflective crystalline layers using a low temperature seeding layer
01/25/2000US6016947 Non-destructive low melt test for off-composition solder
01/25/2000US6016852 Leaded grid array IC package having coplanar bent leads for surface mount technology
01/25/2000US6016765 Plasma processing apparatus
01/25/2000US6016612 Process and device for drying of substrates
01/25/2000US6016611 Gas flow control in a substrate processing system
01/25/2000CA2000431C A method of preparing thin layers of conductive polymers
01/20/2000WO2000003576A2 Process and apparatus for manufacturing semiconductor devices
01/20/2000WO2000003574A2 Heat sink with transverse ribs
01/20/2000WO2000003572A1 Printed wiring board and method for producing the same
01/20/2000WO2000003571A1 Method for producing interconnections with electrically conductive cross connections between the top and the bottom part of a substrate and interconnections having such cross connections
01/20/2000WO2000003569A1 Interconnect assembly for printed circuit boards and method of fabrication
01/20/2000WO2000003566A1 Microwave discharge apparatus
01/20/2000WO2000003467A2 Wafer carrier and method for handling of wafers with minimal contact
01/20/2000WO2000003440A1 Silicon carbide horizontal channel buffered gate semiconductor devices
01/20/2000WO2000003437A1 Circuit and a method for the production thereof
01/20/2000WO2000003433A1 Misalignment tolerant techniques for dual damascene fabrication
01/20/2000WO2000003432A1 Plasma etch process of a dielectric multilayer structure particularly useful for dual damascene
01/20/2000WO2000003431A1 Method of forming metal interconnects
01/20/2000WO2000003430A1 Methods of forming silicon dioxide layers, and methods of forming trench isolation regions
01/20/2000WO2000003429A1 Thin-layered semiconductor structure comprising a heat distribution layer
01/20/2000WO2000003428A1 Substrate transfer device and operating method thereof
01/20/2000WO2000003427A1 Semiconductor power device manufacture
01/20/2000WO2000003426A1 Methods and apparatus for electropolishing metal interconnections on semiconductor devices
01/20/2000WO2000003425A1 Plasma process to deposit silicon nitride with high film quality and low hydrogen content
01/20/2000WO2000003424A1 Two-step integrated self aligned contact etch
01/20/2000WO2000003423A1 System and method for producing and supplying highly clean dry air
01/20/2000WO2000003422A2 Gas flow control in a substrate processing system
01/20/2000WO2000003421A2 Improved endpoint detection for substrate fabrication processes
01/20/2000WO2000003420A2 Method for forming a copper film on a substrate