Patents
Patents for H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof (658,974)
02/2000
02/15/2000US6025618 Two-parts ferroelectric RAM
02/15/2000US6025617 Microelectronic devices having increased impurity concentration between a metal silicide contact surface
02/15/2000US6025615 Microwave heterojunction bipolar transistors with emitters designed for high power applications and method for fabricating same
02/15/2000US6025614 Amplifier semiconductor element, method for fabricating the same, and amplifier semiconductor device
02/15/2000US6025613 Semiconductor device capable of reducing leak current and having excellent pinch-off characteristic and method of manufacturing the same
02/15/2000US6025612 NAND or NOR compound semiconductor memory
02/15/2000US6025609 Laser synthesized ceramic electronic devices and circuits and method for making
02/15/2000US6025607 Thin-film transistor and liquid crystal display device
02/15/2000US6025605 Aligned semiconductor structure
02/15/2000US6025604 Fine projection structure and fabricating method thereof
02/15/2000US6025602 Ion implantation system for implanting workpieces
02/15/2000US6025596 Method for measuring epitaxial film thickness of multilayer epitaxial wafer
02/15/2000US6025575 Heating apparatus for chemical vapor deposition equipment
02/15/2000US6025281 Applying molecular, atomic, or isotopic species during oxide deposition in ultrahigh vacuum to reduce interface state density
02/15/2000US6025280 Use of SiD4 for deposition of ultra thin and controllable oxides
02/15/2000US6025279 Method of reducing nitride and oxide peeling after planarization using an anneal
02/15/2000US6025278 Methods for manufacturing semiconductive wafers and semiconductive material stencil masks
02/15/2000US6025277 Method and structure for preventing bonding pad peel back
02/15/2000US6025276 Semiconductor processing methods of forming substrate features, including contact openings
02/15/2000US6025275 Forming bonds directly on thick plated interconnect, eliminating high parasitic series resistance associated with bond pads
02/15/2000US6025274 Providing substrate with gate, forming spacer having middle indented waistline on side wall of gate, forming metal layer having gap at indentation, transforming metal into silicide
02/15/2000US6025273 Carbon atoms released from carbon doped polysilicon hard mask during contact hole etching reduce free oxygen and contamination buildup and increase etch rate of dielectric layer
02/15/2000US6025272 Method of planarize and improve the effectiveness of the stop layer
02/15/2000US6025271 Method of removing surface defects or other recesses during the formation of a semiconductor device
02/15/2000US6025270 Planarization process using tailored etchback and CMP
02/15/2000US6025269 Method for depositioning a substantially void-free aluminum film over a refractory metal nitride layer
02/15/2000US6025268 Method of etching conductive lines through an etch resistant photoresist mask
02/15/2000US6025267 Silicon nitride--TEOS oxide, salicide blocking layer for deep sub-micron devices
02/15/2000US6025266 Controlling formation of film on backside of wafer, using moveable cover shield
02/15/2000US6025265 Method of forming a landing pad structure in an integrated circuit
02/15/2000US6025264 Forming organic low-k dielectric layer over conductive layer on semiconductor substrate, forming opening, forming doped silicon barrier layer over sides, depositing second barrier layer and conductive layer, polishing to expose dielectric
02/15/2000US6025263 Defining metal line pattern on semiconductor surface, depositing dielectric underlayer of silicon dioxide with constant refraction index, forming interlayer dielectric using ozone and tetraethyl orthosilicate
02/15/2000US6025262 Patterning to produce conductive runners, applying passivation layer of silicon dioxide, planarizing by chemical mechanical polishing, applying overcoating layer of silicon nitride, etching to bonding pads associated with runners
02/15/2000US6025261 Method for making high-Q inductive elements
02/15/2000US6025260 Method for fabricating air gap with borderless contact
02/15/2000US6025259 Dual damascene process using high selectivity boundary layers
02/15/2000US6025258 Method for fabricating solder bumps by forming solder balls with a solder ball forming member
02/15/2000US6025257 Forming metal film and dielectric film which contains perovskite type oxide on substrate, annealing so metal oxidizes and diffuses into crystal structure of dielectric
02/15/2000US6025256 Laser based method and system for integrated circuit repair or reconfiguration
02/15/2000US6025255 Initially etching contact opening at high selectivity, then, as contact channel narrows, reducing polymer formation rate to prevent polymer pinch off and assure insulator clearance
02/15/2000US6025254 Low resistance gate electrode layer and method of making same
02/15/2000US6025253 Differential poly-edge oxidation for stable SRAM cells
02/15/2000US6025251 Method for producing a plurality of semiconductor components
02/15/2000US6025250 Methods including wafer grooves for reducing semiconductor wafer warping and related structure
02/15/2000US6025249 Method for manufacturing shallow trench isolation structure
02/15/2000US6025248 Methods of forming capacitor electrodes including a capacitor electrode etch
02/15/2000US6025247 Method for manufacturing capacitor structure of dynamic memory cell
02/15/2000US6025246 Methods for fabricating microelectronic capacitor structures
02/15/2000US6025245 Method of forming a trench capacitor with a sacrificial silicon nitrate sidewall
02/15/2000US6025244 Self-aligned patterns by chemical-mechanical polishing particularly suited to the formation of MCM capacitors
02/15/2000US6025243 Feeding gas of hexamethylmolybdenum and hydrogen gas onto substrate to deposit molybdenum in opening forming barrier metal, forming aluminum film thereon for electrical wiring
02/15/2000US6025242 Fabrication of semiconductor device having shallow junctions including an insulating spacer by thermal oxidation creating taper-shaped isolation
02/15/2000US6025241 Method of fabricating semiconductor devices with self-aligned silicide
02/15/2000US6025240 Method and system for using a spacer to offset implant damage and reduce lateral diffusion in flash memory devices
02/15/2000US6025238 Using nitrogen-rich punchthrough region to inhibit diffusion of dopants used in forming channel region
02/15/2000US6025237 Methods of forming field effect transistors having graded drain region doping profiles therein
02/15/2000US6025236 Methods of forming field oxide and active area regions on a semiconductive substrate
02/15/2000US6025235 Short channel transistor having resistive gate extensions
02/15/2000US6025234 Method for manufacturing thick gate oxide device
02/15/2000US6025233 Method of manufacturing a semiconductor device
02/15/2000US6025232 Methods of forming field effect transistors and related field effect transistor constructions
02/15/2000US6025230 High speed MOSFET power device with enhanced ruggedness fabricated by simplified processes
02/15/2000US6025229 Method of fabricating split-gate source side injection flash memory array
02/15/2000US6025228 Providing a first polysilicon layer, providing high dielectric constant layer, forming oxynitride layer
02/15/2000US6025227 Capacitor over bit line structure using a straight bit line shape
02/15/2000US6025226 Method of forming a capacitor and a capacitor formed using the method
02/15/2000US6025225 Circuits with a trench capacitor having micro-roughened semiconductor surfaces and methods for forming the same
02/15/2000US6025224 Device with asymmetrical channel dopant profile
02/15/2000US6025223 Methods of forming high dielectric capacitors
02/15/2000US6025222 Vapor phase growth of a dielectric film and a fabrication process of a semiconductor device having such a dielectric film
02/15/2000US6025221 Processing methods of forming integrated circuitry memory devices, methods of forming DRAM arrays, and related semiconductor masks
02/15/2000US6025220 Method of forming a polysilicon diode and devices incorporating such diode
02/15/2000US6025219 Method of manufacturing a semiconductor device having MOS transistor and bipolar transistor in mixture on the same substrate
02/15/2000US6025218 Method of manufacturing a thin-film electronic device with a laminated conductor
02/15/2000US6025217 Forming uniform polycrystalline semiconductor thin film by laser annealing amorphous film
02/15/2000US6025216 TET-LCD method for manufacturing the same
02/15/2000US6025215 Method of making field effect transistors
02/15/2000US6025211 Setting surface other than element forming region to be non-hydrogen-terminated insulating region, isolating elements formed thereon
02/15/2000US6025206 Method for detecting defects
02/15/2000US6025205 Apparatus and methods of forming preferred orientation-controlled platinum films using nitrogen
02/15/2000US6025116 Etching of contact holes
02/15/2000US6025115 Selectively irradiating surface of substrate with light in gas atmosphere to form surface-modified layer, annealing to stabilize and make more etch resistant, dry etching non-modified portion
02/15/2000US6025113 Photosensitve polymide precursor and its use for pattern formation
02/15/2000US6025099 Exposure of photoresists on substrates to form images
02/15/2000US6024888 Etching at room temperature silicon oxide layers formed on a wafer in a gaseous etching atmosphere consisting essentially of a mixture of hydrogen fluoride and water vapor
02/15/2000US6024887 Useful for stripping from semiconductor substrates ion implanted patterned photoresist layers
02/15/2000US6024885 Process for patterning magnetic films
02/15/2000US6024856 Copper metallization of silicon wafers using insoluble anodes
02/15/2000US6024844 Enhanced reactive DC sputtering system
02/15/2000US6024829 Eliminating agglomerate particles in a polishing slurry used for polishing a semiconductor wafer
02/15/2000US6024828 Spin-on-glass etchback uniformity improvement using hot backside helium
02/15/2000US6024826 Plasma reactor with heated source of a polymer-hardening precursor material
02/15/2000US6024802 Vapor treatment process for reducing oxide depletion
02/15/2000US6024801 Exposing device surface in an enclosure to supercritical fluid cleaning medium, purging of libeated substances, depositing lubrication passivant, removing device
02/15/2000US6024800 Plasma processing apparatus
02/15/2000US6024794 Determination of critical film thickness of a compound semiconductor layer, and a method for manufacturing a semiconductor device using the method of determination
02/15/2000US6024631 Method and apparatus to hold integrated circuit chips onto a chuck and to simultaneously remove multiple integrated circuit chips from a cutting chuck
02/15/2000US6024630 Fluid-pressure regulated wafer polishing head
02/15/2000US6024629 Probe apparatus and a method for polishing a probe
02/15/2000US6024620 Field emission displays with reduced light leakage