| Patents for H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof (658,974) |
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| 02/01/2000 | US6021081 Semiconductor memory device having strobe buffer and output buffer |
| 02/01/2000 | US6021080 Semiconductor memory device having a voltage converting circuit |
| 02/01/2000 | US6021065 Spin dependent tunneling memory |
| 02/01/2000 | US6021061 Semiconductor memory device |
| 02/01/2000 | US6020968 Method of and apparatus for inspecting residue of metal film |
| 02/01/2000 | US6020964 Interferometer system and lithograph apparatus including an interferometer system |
| 02/01/2000 | US6020957 System and method for inspecting semiconductor wafers |
| 02/01/2000 | US6020781 Step-up circuit using two frequencies |
| 02/01/2000 | US6020780 Substrate potential control circuit capable of making a substrate potential change in response to a power-supply voltage |
| 02/01/2000 | US6020755 Hybrid programmable gate arrays |
| 02/01/2000 | US6020749 Method and apparatus for performing testing of double-sided ball grid array devices |
| 02/01/2000 | US6020746 Method and apparatus for probing an integrated circuit through the back side of an integrated circuit die |
| 02/01/2000 | US6020710 Exposure method, and method of making exposure apparatus having dynamically isolated reaction frame |
| 02/01/2000 | US6020686 Inductively and multi-capacitively coupled plasma reactor |
| 02/01/2000 | US6020649 Plastic molded semiconductor package and a method for producing the same |
| 02/01/2000 | US6020646 Intergrated circuit die assembly |
| 02/01/2000 | US6020645 Semiconductor device with semiconductor chip bonded face down on circuit-carrying substrate |
| 02/01/2000 | US6020644 Semiconductor memory device having bit lines and signal wiring layers different in thickness and process of fabricating thereof |
| 02/01/2000 | US6020643 Semiconductor memory device having contact holes of differing structure |
| 02/01/2000 | US6020642 Interconnection system in a semiconductor device |
| 02/01/2000 | US6020641 Multilevel interconnection with low contact resistance in a semiconductor device |
| 02/01/2000 | US6020640 Thick plated interconnect and associated auxillary interconnect |
| 02/01/2000 | US6020639 Semiconductor wafer with removed CVD copper |
| 02/01/2000 | US6020630 Tape automated bonding package for a semiconductor chip employing corner member cross-slots |
| 02/01/2000 | US6020628 Optical component package with a hermetic seal |
| 02/01/2000 | US6020624 Semiconductor package with bi-substrate die |
| 02/01/2000 | US6020622 Trench isolation for semiconductor device with lateral projections above substrate |
| 02/01/2000 | US6020621 Stress-free shallow trench isolation |
| 02/01/2000 | US6020620 Semiconductor light-receiving device with inclined multilayer structure |
| 02/01/2000 | US6020618 Semiconductor device in which thin silicon portions are formed by electrochemical stop etching method |
| 02/01/2000 | US6020617 Lateral MOS transistor with weakly doped drain extension |
| 02/01/2000 | US6020616 Automated design of on-chip capacitive structures for suppressing inductive noise |
| 02/01/2000 | US6020615 Semiconductor-on-insulator devices including alternating thin and thick film semiconductor stripes on an insulating layer |
| 02/01/2000 | US6020614 Method of reducing substrate noise coupling in mixed signal integrated circuits |
| 02/01/2000 | US6020613 Field effect transistor array including resistive interconnections |
| 02/01/2000 | US6020612 Semiconductor integrated circuit having efficient layout of wiring lines |
| 02/01/2000 | US6020611 Semiconductor component and method of manufacture |
| 02/01/2000 | US6020610 Semiconductor device and method of manufacturing the same |
| 02/01/2000 | US6020609 DRAM cell with a rugged stacked trench (RST) capacitor |
| 02/01/2000 | US6020608 Junction-type field-effect transistor with improved impact-ionization resistance |
| 02/01/2000 | US6020607 Semiconductor device having junction field effect transistors |
| 02/01/2000 | US6020606 Structure of a memory cell |
| 02/01/2000 | US6020604 Compound semiconductor device |
| 02/01/2000 | US6020600 Silicon carbide semiconductor device with trench |
| 02/01/2000 | US6020599 Liquid crystal display having separable gate lines and gate shorting bar when the connection portion is oxidized |
| 02/01/2000 | US6020598 Liquid crystal display device including crossing gate wiring |
| 02/01/2000 | US6020592 Dose monitor for plasma doping system |
| 02/01/2000 | US6020570 Plasma processing apparatus |
| 02/01/2000 | US6020561 Printed circuit substrate with solder formed on pad-on-via and pad-off-via contacts thereof |
| 02/01/2000 | US6020511 Methods, complexes, and systems for forming metal-containing films |
| 02/01/2000 | US6020458 Precursors for making low dielectric constant materials with improved thermal stability |
| 02/01/2000 | US6020292 Aqueous solution containing a quaternary ammonium hydroxide and corrosion inhibitor |
| 02/01/2000 | US6020274 Reduction of defects at interface |
| 02/01/2000 | US6020273 Forming patterned layer of conductor on substrate; then dielectric; nitriding |
| 02/01/2000 | US6020271 Manufacturing method of semiconductor device |
| 02/01/2000 | US6020270 Bomine and iodine etch process for silicon and silicides |
| 02/01/2000 | US6020269 Ultra-thin resist and nitride/oxide hard mask for metal etch |
| 02/01/2000 | US6020268 Magnetic field controlled spacer width |
| 02/01/2000 | US6020267 Method for forming local interconnect metal structures via the addition of a titanium nitride anti-reflective coating |
| 02/01/2000 | US6020266 Single step electroplating process for interconnect via fill and metal line patterning |
| 02/01/2000 | US6020265 Method for forming a planar intermetal dielectric layer |
| 02/01/2000 | US6020264 Method and apparatus for in-line oxide thickness determination in chemical-mechanical polishing |
| 02/01/2000 | US6020262 Methods and apparatus for chemical mechanical planarization (CMP) of a semiconductor wafer |
| 02/01/2000 | US6020261 Process for forming high aspect ratio circuit features |
| 02/01/2000 | US6020260 Annealing polysilicon layer in nitrogen |
| 02/01/2000 | US6020259 Method of forming a tungsten-plug contact for a semiconductor device |
| 02/01/2000 | US6020258 Method for unlanded via etching using etch stop |
| 02/01/2000 | US6020257 Membrane dielectric isolation IC fabrication |
| 02/01/2000 | US6020256 Method of integrated circuit fabrication |
| 02/01/2000 | US6020255 Dual damascene interconnect process with borderless contact |
| 02/01/2000 | US6020254 Forming contact apertures in dielectric; filling with electroconductive material; removal surface damage |
| 02/01/2000 | US6020253 Decomposition; phosphiding |
| 02/01/2000 | US6020252 Doping by bombardment |
| 02/01/2000 | US6020251 Method of forming buried diffusion junctions in conjunction with shallow-trench isolation structures in a semiconductor device |
| 02/01/2000 | US6020250 Stacked devices |
| 02/01/2000 | US6020248 Method for fabricating semiconductor device having capacitor increased in capacitance by using hemispherical grains without reduction of dopant concentration |
| 02/01/2000 | US6020247 Multilayer oxidation; removal excess in vacuum; heating; annealing |
| 02/01/2000 | US6020246 Forming a self-aligned epitaxial base bipolar transistor |
| 02/01/2000 | US6020245 Method of manufacturing semiconductor device where characteristics can be measured at manufacture |
| 02/01/2000 | US6020244 Channel dopant implantation with automatic compensation for variations in critical dimension |
| 02/01/2000 | US6020243 Zirconium and/or hafnium silicon-oxynitride gate dielectric |
| 02/01/2000 | US6020242 Effective silicide blocking |
| 02/01/2000 | US6020241 Post metal code engineering for a ROM |
| 02/01/2000 | US6020240 Method to simultaneously fabricate the self-aligned silicided devices and ESD protection devices |
| 02/01/2000 | US6020239 Pillar transistor incorporating a body contact |
| 02/01/2000 | US6020238 Forming dielectric layers on polycrystalline silicon |
| 02/01/2000 | US6020237 Method of reducing dielectric damage due to charging in the fabrication of stacked gate structures |
| 02/01/2000 | US6020236 Method to form capacitance node contacts with improved isolation in a DRAM process |
| 02/01/2000 | US6020234 Increasing capacitance for high density DRAM by microlithography patterning |
| 02/01/2000 | US6020233 Ferroelectric memory device guaranteeing electrical interconnection between lower capacitor electrode and contact plug and method for fabricating the same |
| 02/01/2000 | US6020232 Process of fabricating transistors having source and drain regions laterally displaced from the transistors gate |
| 02/01/2000 | US6020231 Method for forming LDD CMOS |
| 02/01/2000 | US6020230 Process to fabricate planarized deep-shallow trench isolation having upper and lower portions with oxidized semiconductor trench fill in the upper portion and semiconductor trench fill in the lower portion |
| 02/01/2000 | US6020229 Semiconductor device method for manufacturing |
| 02/01/2000 | US6020228 CMOS device structure with reduced short channel effect and memory capacitor |
| 02/01/2000 | US6020227 Fabrication of multiple field-effect transistor structure having local threshold-adjust doping |
| 02/01/2000 | US6020226 In semiconductor wafer |
| 02/01/2000 | US6020225 Method of manufacturing array substrate of a liquid crystal display device |
| 02/01/2000 | US6020224 Method for making thin film transistor |
| 02/01/2000 | US6020223 Method of manufacturing a thin film transistor with reduced parasitic capacitance and reduced feed-through voltage |