Patents
Patents for H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof (658,974)
04/2000
04/18/2000US6052193 Apparatus and method for inspecting loading state of wafers in carrier
04/18/2000US6052189 Height measurement device and height measurement method
04/18/2000US6052185 Method and apparatus for measuring the concentration of ions implanted in semiconductor materials
04/18/2000US6052178 Method for aligning optical elements one another on V-groove substrate
04/18/2000US6052176 Processing chamber with optical window cleaned using process gas
04/18/2000US6052173 Device for exposing the peripheral area of a wafer
04/18/2000US6052168 Active matrix liquid-crystal display with verticle alignment, positive anisotropy and opposing electrodes below pixel electrode
04/18/2000US6052074 Multi-channel digital-to-analog converters comprising with a plurality of converter units
04/18/2000US6052025 CMOS operational amplifiers having reduced power consumption requirements and improved phase margin characteristics
04/18/2000US6052022 Voltage boosting circuits having over-voltage protection circuits therein
04/18/2000US6052014 Integrated circuit being capable of transferring signals of different voltage levels between its input and output
04/18/2000US6051968 Test board provided with a capacitor charging circuit and related test method
04/18/2000US6051889 Semiconductor device having a flip-chip structure
04/18/2000US6051885 Semiconductor device having a conductor with a wedge shaped depression
04/18/2000US6051884 Method of forming interconnections in an integrated circuit
04/18/2000US6051883 Manufacturing method and semiconductor device with low contact resistance between transparent electrode and pad electrode
04/18/2000US6051882 Subtractive dual damascene semiconductor device
04/18/2000US6051880 Base layer structure covering a hole of decreasing diameter in an insulation layer in a semiconductor device
04/18/2000US6051879 Electrical interconnection for attachment to a substrate
04/18/2000US6051878 Method of constructing stacked packages
04/18/2000US6051877 Semiconductor device and fabrication method
04/18/2000US6051875 Semiconductor chip
04/18/2000US6051873 Semiconductor device including self-aligned base and emitter electrodes
04/18/2000US6051872 Semiconductor integration device and fabrication method of the same
04/18/2000US6051870 Process for fabricating semiconductor device including improved phosphorous-doped silicon dioxide dielectric film
04/18/2000US6051869 Silicon-rich block copolymers to achieve unbalanced vias
04/18/2000US6051868 Semiconductor device
04/18/2000US6051867 Interlayer dielectric for passivation of an elevated integrated circuit sensor structure
04/18/2000US6051866 Microstructures and single mask, single-crystal process for fabrication thereof
04/18/2000US6051865 Transistor having a barrier layer below a high permittivity gate dielectric
04/18/2000US6051864 Memory masking for periphery salicidation of active regions
04/18/2000US6051863 Transistor gate conductor having sidewall surfaces upon which a spacer having a profile that substantially prevents silicide bridging is formed
04/18/2000US6051862 MOS-technology power device integrated structure
04/18/2000US6051861 Semiconductor device with reduced fringe capacitance and short channel effect
04/18/2000US6051860 Nonvolatile semiconductor memory device and method for fabricating the same and semiconductor integrated circuit
04/18/2000US6051859 DRAM having a cup-shaped storage node electrode recessed within an insulating layer
04/18/2000US6051858 Ferroelectric/high dielectric constant integrated circuit and method of fabricating same
04/18/2000US6051856 Voltage-controlled resistor utilizing bootstrap gate FET
04/18/2000US6051851 Semiconductor devices utilizing silicide reaction
04/18/2000US6051850 Insulated gate bipolar junction transistors having built-in freewheeling diodes therein
04/18/2000US6051849 Gallium nitride semiconductor structures including a lateral gallium nitride layer that extends from an underlying gallium nitride layer
04/18/2000US6051846 Monolithic integrated high-Tc superconductor-semiconductor structure
04/18/2000US6051845 Method and apparatus for selectively marking a semiconductor wafer
04/18/2000US6051843 Exposure apparatus and method which synchronously moves the mask and the substrate to measure displacement
04/18/2000US6051842 Illumination optical apparatus with optical integrator
04/18/2000US6051841 Plasma focus high energy photon source
04/18/2000US6051823 Method and apparatus to compensate for non-uniform film growth during chemical vapor deposition
04/18/2000US6051815 Apparatus for heat-treating substrate and method for separating the substrate from the apparatus
04/18/2000US6051778 Electrode structure, process production thereof and photo-electricity generating device including the electrode
04/18/2000US6051625 Benzoin ethers of given formula which generate free radicals upon ultraviolet exposure, and free radical polymerizable poly(silsesquioxane-silicate-siloxane) containing vinylphenyl groups; storage stable, air or oxygen does not inhibit curing
04/18/2000US6051512 Apparatus and method for rapid thermal processing (RTP) of a plurality of semiconductor wafers
04/18/2000US6051511 Method and apparatus for reducing isolation stress in integrated circuits
04/18/2000US6051510 Method of using a hard mask to grow dielectrics with varying characteristics
04/18/2000US6051509 Semiconductor integrated circuit manufacturing method and device
04/18/2000US6051508 Manufacturing method of semiconductor device
04/18/2000US6051507 Method of fabricating capacitor with high capacitance
04/18/2000US6051506 Method of fabrication ultra-frequency semiconductor device
04/18/2000US6051505 Microelectronics; forming via through silicon
04/18/2000US6051504 Anisotropic and selective nitride etch process for high aspect ratio features in high density plasma
04/18/2000US6051503 Method of surface treatment of semiconductor substrates
04/18/2000US6051502 Forming blocking layer; anisotropically etching conductive shape
04/18/2000US6051501 Method of reducing overetch during the formation of a semiconductor device
04/18/2000US6051500 Device and method for polishing a semiconductor substrate
04/18/2000US6051499 Rotation
04/18/2000US6051498 Method for manufacturing a semiconductor wafer which is coated on one side and provided with a finish
04/18/2000US6051497 Formation of sub-groundrule features
04/18/2000US6051496 Use of stop layer for chemical mechanical polishing of CU damascene
04/18/2000US6051495 Comprising a supports and a seasoning layer attached to the first surface of the support device, for seasoning a polishing pad with tungsten polishing by-product to polish tungsten
04/18/2000US6051494 Semiconductor device having metal silicide film
04/18/2000US6051493 Process for protecting bonded components from plating shorts
04/18/2000US6051492 Plasma pretreating the dielectric layer with radio frequency or electron cyclotron resonance non-active gas, depositing a tungsten nitride film in the contact hole
04/18/2000US6051491 Multilevel interconnection structure for integrated circuits and method of producing same
04/18/2000US6051490 Method of forming wirings
04/18/2000US6051488 Methods of forming semiconductor switching devices having trench-gate electrodes
04/18/2000US6051487 Semiconductor device fabrication using a sacrificial plug for defining a region for a gate electrode
04/18/2000US6051486 Method and structure for replaceable gate electrode in insulated gate field effect transistors
04/18/2000US6051485 Photomask the silicon oxide layer, etching the silicon oxide layer, applying a platinum-metal layer to the mask and the exposed substrate surface area, etching to remove the silicon oxide layer and platinum metal on the mask surface area
04/18/2000US6051484 Semiconductor device and method of manufacturing thereof
04/18/2000US6051483 Formation of ultra-shallow semiconductor junction using microwave annealing
04/18/2000US6051482 Method for manufacturing buried-channel PMOS
04/18/2000US6051480 Trench isolation for semiconductor devices
04/18/2000US6051479 Method of fabricating shallow trench isolation
04/18/2000US6051478 Method of enhancing trench edge oxide quality
04/18/2000US6051477 Method of fabricating semiconductor device
04/18/2000US6051476 Method for manufacturing capacitor of semiconductor memory device
04/18/2000US6051475 Method for manufacturing a silicide to silicide capacitor
04/18/2000US6051474 Negative biasing of isolation trench fill to attract mobile positive ions away from bipolar device regions
04/18/2000US6051473 Fabrication of raised source-drain transistor devices
04/18/2000US6051472 Semiconductor device and method of producing the same
04/18/2000US6051471 Method for making asymmetrical N-channel and symmetrical P-channel devices
04/18/2000US6051470 Dual-gate MOSFET with channel potential engineering
04/18/2000US6051469 Method of fabricating bit line
04/18/2000US6051468 Method of forming a semiconductor structure with uniform threshold voltage and punch-through tolerance
04/18/2000US6051467 Method to fabricate a large planar area ONO interpoly dielectric in flash device
04/18/2000US6051466 Method of making a semiconductor device with a stacked cell structure
04/18/2000US6051465 Method for fabricating nonvolatile semiconductor memory device
04/18/2000US6051464 Method for fabricating a capacitor of a DRAM with an HSG layer
04/18/2000US6051463 Method fabricating a data-storage capacitor for a dynamic random-access memory device
04/18/2000US6051462 Process for producing semiconductor device comprising a memory element and a logic element
04/18/2000US6051460 Preventing boron penetration through thin gate oxide of P-channel devices by doping polygate with silicon