| Patents for H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof (658,974) |
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| 08/22/2000 | US6107193 Using dry etching step employing hydrochloric acid/chlorine plasma |
| 08/22/2000 | US6107192 Reactive preclean prior to metallization for sub-quarter micron application |
| 08/22/2000 | US6107191 Method of creating an interconnect in a substrate and semiconductor device employing the same |
| 08/22/2000 | US6107190 Forming an interlayer insulating film on a semiconductor substrate, forming a first titanium nitride film on the interlayer insulating film by sputtering, forming a hole throughout the interlayer insulating film |
| 08/22/2000 | US6107189 Method of making a local interconnect using spacer-masked contact etch |
| 08/22/2000 | US6107188 Providing semiconductor substrate having layer of first dielectric formed thereon, forming layer of second dielectric on first dielectric, forming copper conductors imbedded in second dielectric, forming passivation layer, etch stop |
| 08/22/2000 | US6107187 Method for forming a semiconductor device |
| 08/22/2000 | US6107186 High planarity high-density in-laid metallization patterns by damascene-CMP processing |
| 08/22/2000 | US6107185 Conductive material adhesion enhancement in damascene process for semiconductors |
| 08/22/2000 | US6107184 Nano-porous copolymer films having low dielectric constants |
| 08/22/2000 | US6107183 Method of forming an interlevel dielectric |
| 08/22/2000 | US6107182 Forming first and second aluminum or aluminum alloy layers as conductive substance for connection through-holes |
| 08/22/2000 | US6107181 Method of forming bumps and template used for forming bumps |
| 08/22/2000 | US6107180 Forming a seed layer over the bump pads, then copper, then tin layer using evaporation process covering copper layer, forming lead stand-off structure, depositing eutectic layer of tin-lead solder over bump pads and reflowing the eutectic |
| 08/22/2000 | US6107178 Methods for etching fuse openings in a semiconductor device |
| 08/22/2000 | US6107177 Silylation method for reducing critical dimension loss and resist loss |
| 08/22/2000 | US6107176 Forming a polysilicon layer on oxide layer, doping a barrier matal ion into upper surface of polysilicon, forming aconductive layer on doped polysilicon, annealing to form barrier from a reaction between barrier matal and polysilicon |
| 08/22/2000 | US6107175 Method of fabricating self-aligned contact |
| 08/22/2000 | US6107174 Gate dielectric silicon oxynitride film is made by nitriting the thermal oxide film by introducing nitrogen from top surface |
| 08/22/2000 | US6107173 Method of manufacturing semiconductor device |
| 08/22/2000 | US6107172 Forming a conductive layer on a semiconductor substrate that uses a silicon oxynitride film as a bottom anti-reflective coating, isotropic etching further trim the resist mask before etching through one or more underlying layers in wafer stack |
| 08/22/2000 | US6107171 Method to manufacture metal gate of integrated circuits |
| 08/22/2000 | US6107169 Method for fabricating a doped polysilicon feature in a semiconductor device |
| 08/22/2000 | US6107168 Process for passivating a silicon carbide surface against oxygen |
| 08/22/2000 | US6107167 Simplified method of patterning polysilicon gate in a semiconductor device |
| 08/22/2000 | US6107166 Vapor phase cleaning of alkali and alkaline earth metals |
| 08/22/2000 | US6107164 Using grooves as alignment marks when dicing an encapsulated semiconductor wafer |
| 08/22/2000 | US6107163 Method of manufacturing a semiconductor chip |
| 08/22/2000 | US6107162 Forming a semiconductor layer on one surface of a sapphire substrate, forming grooves in a surface opposite of substrate surface in such a shape as to concentrate stress at bottom portion of the groove, breaking the substrate at groove |
| 08/22/2000 | US6107161 Semiconductor chip and a method for manufacturing thereof |
| 08/22/2000 | US6107159 Method for fabricating a shallow trench isolation structure |
| 08/22/2000 | US6107158 Helium, oxygen, chlorine, and hydrogen bromide are introduced into an etching environment a semiconductor substrate is then etched, until a trench of desired depth is formed in the substrate, adding an oxygen echant, etching to form a trench |
| 08/22/2000 | US6107157 Etching trench through nitride, polysilicon gate and gate oxide, the trench extending to the substrate, filling the trench with field oxide, planarizing the field oxide through chemical-mechanical planrization, removing nitride stop layer |
| 08/22/2000 | US6107156 Silicide layer forming method and semiconductor integrated circuit |
| 08/22/2000 | US6107155 Method for making a more reliable storage capacitor for dynamic random access memory (DRAM) |
| 08/22/2000 | US6107154 Method of fabricating a semiconductor embedded dynamic random-access memory device |
| 08/22/2000 | US6107153 Method of forming a trench capacitor for a DRAM cell |
| 08/22/2000 | US6107152 Method of forming tungsten nitride comprising layers using NF3 as a nitrogen source gas |
| 08/22/2000 | US6107151 Suppressing the creation of gallium interstitials which can activate the zinc substitutional-interstitial diffusion mechanism by minimizing n+ doping regions to minimize zinc diffusion |
| 08/22/2000 | US6107150 Implanting nitrogen into a region of a semiconducting substrate, forming a nitrogen bearing silicon oxide gate dielectric above the region in the substrate, forming a gate conductor over the gate dielectric, forming source and drain |
| 08/22/2000 | US6107149 CMOS semiconductor device comprising graded junctions with reduced junction capacitance |
| 08/22/2000 | US6107148 Method for fabricating a semiconductor device |
| 08/22/2000 | US6107147 Stacked poly/amorphous silicon gate giving low sheet resistance silicide film at submicron linewidths |
| 08/22/2000 | US6107146 Method of replacing epitaxial wafers in CMOS process |
| 08/22/2000 | US6107145 Method for forming a field effect transistor |
| 08/22/2000 | US6107144 Method for forming field oxide of semiconductor device and the semiconductor device |
| 08/22/2000 | US6107143 Method for forming a trench isolation structure in an integrated circuit |
| 08/22/2000 | US6107142 Self-aligned methods of fabricating silicon carbide power devices by implantation and lateral diffusion |
| 08/22/2000 | US6107141 Flash EEPROM |
| 08/22/2000 | US6107140 Method of patterning gate electrode conductor with ultra-thin gate oxide |
| 08/22/2000 | US6107139 Method for making a mushroom shaped DRAM capacitor |
| 08/22/2000 | US6107138 Method for fabricating a semiconductor device having a tapered contact hole |
| 08/22/2000 | US6107137 Method of forming a capacitor |
| 08/22/2000 | US6107136 Method for forming a capacitor structure |
| 08/22/2000 | US6107135 Method of making a semiconductor memory device having a buried plate electrode |
| 08/22/2000 | US6107134 High performance DRAM structure employing multiple thickness gate oxide |
| 08/22/2000 | US6107133 Method for making a five square vertical DRAM cell |
| 08/22/2000 | US6107132 Method of manufacturing a DRAM capacitor |
| 08/22/2000 | US6107131 Method of fabricating interpoly dielectric layer of embedded dynamic random access memory |
| 08/22/2000 | US6107130 CMOS integrated circuit having a sacrificial metal spacer for producing graded NMOS source/drain junctions dissimilar from PMOS source/drain junctions |
| 08/22/2000 | US6107129 Integrated circuit having multiple LDD and/or source/drain implant steps to enhance circuit performance |
| 08/22/2000 | US6107128 Semiconductor device and method of manufacturing the same |
| 08/22/2000 | US6107127 Method of making shallow well MOSFET structure |
| 08/22/2000 | US6107126 Method to form different threshold NMOSFETS for read only memory devices |
| 08/22/2000 | US6107125 SOI/bulk hybrid substrate and method of forming the same |
| 08/22/2000 | US6107123 Methods for providing void-free layers for semiconductor assemblies |
| 08/22/2000 | US6107122 Direct die contact (DDC) semiconductor package |
| 08/22/2000 | US6107120 Method of making semiconductor devices having protruding contacts |
| 08/22/2000 | US6107119 Method for fabricating semiconductor components |
| 08/22/2000 | US6107118 Chip-contacting method requiring no contact bumps, and electronic circuit produced in this way |
| 08/22/2000 | US6107117 Applying a solution of poly(3-alkylthiophene) combined with a solvent over the layer of insulating material selected from polyimide, polyester, and polymethyl methacrylate and forming active layer, then forming source and drain electrodes |
| 08/22/2000 | US6107115 Method of manufacturing spatial light modulator and electronic device employing it |
| 08/22/2000 | US6107113 Making stacks of metamorphic layers of semiconductor material having lattice mismatches of several percent between one another or relative to the substrate |
| 08/22/2000 | US6107112 Periodically forming grooves at a surface of an indium phosphide substrate, heating the substrate with a mixture of phosphine and arsine to grow indium-arsenic-phsophide layer in each groove, and forming multilayer; crystalllization |
| 08/22/2000 | US6107110 Method and apparatus for aiming a spray etcher nozzle |
| 08/22/2000 | US6107109 Method for fabricating a semiconductor interconnect with laser machined electrical paths through substrate |
| 08/22/2000 | US6107108 Dosage micro uniformity measurement in ion implantation |
| 08/22/2000 | US6107106 Localized control of integrated circuit parameters using focus ion beam irradiation |
| 08/22/2000 | US6107105 Providing an opening to a diffusion region of an underlying substrate, forming a tintanium nitride layer to make contact with diffusion via the opening, patterning nitride layer into a bottom capacitor plate, forming dilectric and top plate |
| 08/22/2000 | US6107096 Forming high purity thin films having uniform thickness and high reproducibility by chemical vapor deposition using gasified cobalt organic compound and thermal annealing to form cobalt disilicide on diffusion layers and gate electrode |
| 08/22/2000 | US6107013 Exposure method and exposure apparatus using it |
| 08/22/2000 | US6107011 Inserting secondary mask between light source and primary mask, secondary mask comprising optical elements; exposing substantially all of principal image on image receiving surface by creating relative motion between masks |
| 08/22/2000 | US6106995 Antireflective coating material for photoresists |
| 08/22/2000 | US6106981 Forming resist film over surface of mask substrate having light shielding film; exposing to electron beam for forming integrated circuit pattern and alignment mask; removing resist film; repeating procedure with aligned second resist film |
| 08/22/2000 | US6106690 Electroplaner |
| 08/22/2000 | US6106687 Process and diffusion baffle to modulate the cross sectional distribution of flow rate and deposition rate |
| 08/22/2000 | US6106683 Grazing angle plasma polisher (GAPP) |
| 08/22/2000 | US6106680 Apparatus for forming a copper interconnect |
| 08/22/2000 | US6106678 Method of high density plasma CVD gap-filling |
| 08/22/2000 | US6106677 Method of creating low resistance contacts in high aspect ratio openings by resputtering |
| 08/22/2000 | US6106676 Method and apparatus for reactive sputtering employing two control loops |
| 08/22/2000 | US6106664 Clamp for affixing a wafer in an etching chamber |
| 08/22/2000 | US6106663 Semiconductor process chamber electrode |
| 08/22/2000 | US6106662 Method and apparatus for endpoint detection for chemical mechanical polishing |
| 08/22/2000 | US6106634 Preheating |
| 08/22/2000 | US6106630 Ceramic-coated heating assembly for high temperature processing chamber |
| 08/22/2000 | US6106629 Impurity doping apparatus |
| 08/22/2000 | US6106628 Heater unit for chemical vapor deposition systems |
| 08/22/2000 | US6106625 Reactor useful for chemical vapor deposition of titanium nitride |
| 08/22/2000 | US6106621 Cross-section sample staining tool |