| Patents for H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof (658,974) |
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| 09/12/2000 | US6118133 Apparatus and method for observing defect having marks making means |
| 09/12/2000 | US6118128 Alignment mark for electron beam lithography |
| 09/12/2000 | US6118080 Z-axis electrical contact for microelectronic devices |
| 09/12/2000 | US6117799 Deposition of super thin PECVD SiO2 in multiple deposition station system |
| 09/12/2000 | US6117798 Method of spin-on-glass planarization |
| 09/12/2000 | US6117797 Improved method for fabricating a chip on board semiconductor device requiring enhanced heat dissipation such as circuit boards |
| 09/12/2000 | US6117796 Removal of silicon oxide |
| 09/12/2000 | US6117795 Cleaning an integrated circuit substrate that has undergone etching using a post-etch cleaning solution comprising a corrosion inhibiting agent including at least one of a sulfur containing compound, a phosphorus compounds, an azole |
| 09/12/2000 | US6117793 Using silicide cap as an etch stop for multilayer metal process and structures so formed |
| 09/12/2000 | US6117792 Method for manufacturing semiconductor device |
| 09/12/2000 | US6117791 Etchant with selectivity for doped silicon dioxide over undoped silicon dioxide and silicon nitride, processes which employ the etchant, and structures formed thereby |
| 09/12/2000 | US6117790 Method for fabricating a capacitor for a semiconductor memory configuration |
| 09/12/2000 | US6117789 Method of manufacturing thin film resistor layer |
| 09/12/2000 | US6117788 Semiconductor etching methods |
| 09/12/2000 | US6117787 Planarization method for a semiconductor device |
| 09/12/2000 | US6117786 Method for etching silicon dioxide using fluorocarbon gas chemistry |
| 09/12/2000 | US6117785 Multiple etch methods for forming contact holes in microelectronic devices including SOG layers and capping layers thereon |
| 09/12/2000 | US6117784 Process for integrated circuit wiring |
| 09/12/2000 | US6117783 The chemical and mechanical polishing solution comprises a hydroxylamine compound and octyphenyl polyethylene |
| 09/12/2000 | US6117782 Optimized trench/via profile for damascene filling |
| 09/12/2000 | US6117781 Optimized trench/via profile for damascene processing |
| 09/12/2000 | US6117780 Chemical mechanical polishing method with in-line thickness detection |
| 09/12/2000 | US6117779 Endpoint detection method and apparatus which utilize a chelating agent to detect a polishing endpoint |
| 09/12/2000 | US6117778 Semiconductor wafer edge bead removal method and tool |
| 09/12/2000 | US6117777 Chemical mechanical polish (CMP) endpoint detection by colorimetry |
| 09/12/2000 | US6117776 Wafer holder and method of producing a semiconductor wafer |
| 09/12/2000 | US6117775 Polishing method |
| 09/12/2000 | US6117773 Methods of fabricating microelectronic devices having increased impurity concentration between a metal silicide contact surface |
| 09/12/2000 | US6117772 Method and apparatus for blanket aluminum CVD on spherical integrated circuits |
| 09/12/2000 | US6117771 Method for depositing cobalt |
| 09/12/2000 | US6117770 Method for implanting semiconductor conductive layers |
| 09/12/2000 | US6117769 Pad structure for copper interconnection and its formation |
| 09/12/2000 | US6117768 Void-free tungsten-plug contact for ULSI interconnection |
| 09/12/2000 | US6117767 Method of forming an integrated circuit structure |
| 09/12/2000 | US6117766 Method of forming contact plugs in a semiconductor device |
| 09/12/2000 | US6117765 Method of preventing cracks in insulating spaces between metal wiring patterns |
| 09/12/2000 | US6117764 Placing a semiconductor wafer having a surface and a recess into a chamber of a plasma source, a layer of etch resistant material is formed within the recess over the surface of the wafer, removing a portion of etch resistant layer |
| 09/12/2000 | US6117763 Method of manufacturing a semiconductor device with a low permittivity dielectric layer and contamination due to exposure to water |
| 09/12/2000 | US6117762 Method and apparatus using silicide layer for protecting integrated circuits from reverse engineering |
| 09/12/2000 | US6117761 Self-aligned silicide strap connection of polysilicon layers |
| 09/12/2000 | US6117760 Method of making a high density interconnect formation |
| 09/12/2000 | US6117759 Method for multiplexed joining of solder bumps to various substrates during assembly of an integrated circuit package |
| 09/12/2000 | US6117758 Etch removal of aluminum islands during manufacture of semiconductor device wiring layer |
| 09/12/2000 | US6117757 Method of forming landing pads for bit line and node contact |
| 09/12/2000 | US6117756 Method of forming high density and low power flash memories with a high capacitive-coupling ratio |
| 09/12/2000 | US6117755 Method for planarizing the interface of polysilicon and silicide in a polycide structure |
| 09/12/2000 | US6117754 Trench free process for SRAM with buried contact structure |
| 09/12/2000 | US6117753 Method of manufacturing compound semiconductor integrated circuit |
| 09/12/2000 | US6117752 Method of manufacturing polycrystalline semiconductor thin film |
| 09/12/2000 | US6117751 Method for manufacturing a mis structure on silicon carbide (SiC) |
| 09/12/2000 | US6117750 Chemical vapour depositing a layer of single-crystal germanium on substrate of single crystal silicon using mixture of silicon and germenium precursor gases and maintaining the desired temperature and weight ratios |
| 09/12/2000 | US6117749 Modification of interfacial fields between dielectrics and semiconductors |
| 09/12/2000 | US6117748 Dishing free process for shallow trench isolation |
| 09/12/2000 | US6117747 Integration of MOM capacitor into dual damascene process |
| 09/12/2000 | US6117744 Method of fabricating semiconductor device |
| 09/12/2000 | US6117743 Method of manufacturing MOS device using anti reflective coating |
| 09/12/2000 | US6117742 Method for making a high performance transistor |
| 09/12/2000 | US6117741 Method of forming a transistor having an improved sidewall gate structure |
| 09/12/2000 | US6117740 Forming shallow trench isolation by using a plasma enhanced deposition of metal oxide and metal nitride, chemical mechanical polishing the multilayer, the multilayer acts as sacrificaal layer to planarize the whole wafer |
| 09/12/2000 | US6117739 Semiconductor device with layered doped regions and methods of manufacture |
| 09/12/2000 | US6117738 Method for fabricating a high-bias semiconductor device |
| 09/12/2000 | US6117737 Reduction of a hot carrier effect by an additional furnace anneal increasing transient enhanced diffusion for devices comprised with low temperature spacers |
| 09/12/2000 | US6117736 Method of fabricating insulated-gate field-effect transistors having different gate capacitances |
| 09/12/2000 | US6117735 Silicon carbide vertical FET and method for manufacturing the same |
| 09/12/2000 | US6117734 Method of forming a trench MOS gate on a power semiconductor device |
| 09/12/2000 | US6117733 Poly tip formation and self-align source process for split-gate flash cell |
| 09/12/2000 | US6117732 Use of a metal contact structure to increase control gate coupling capacitance for a single polysilicon non-volatile memory cell |
| 09/12/2000 | US6117731 Method of forming high capacitive-coupling ratio and high speed flash memories with a textured tunnel oxide |
| 09/12/2000 | US6117730 Integrated method by using high temperature oxide for top oxide and periphery gate oxide |
| 09/12/2000 | US6117729 Nonvolatile semiconductor storage device and its manufacturing method |
| 09/12/2000 | US6117728 Programmable non-volatile memory cell and method of forming a non-volatile memory cell |
| 09/12/2000 | US6117727 Manufacturing process of capacitor |
| 09/12/2000 | US6117726 Method of making a trench capacitor |
| 09/12/2000 | US6117725 Method for making cost-effective embedded DRAM structures compatible with logic circuit processing |
| 09/12/2000 | US6117724 DRAM cell and method of fabricating the same |
| 09/12/2000 | US6117723 Salicide integration process for embedded DRAM devices |
| 09/12/2000 | US6117721 Semiconductor processing method of forming a static random access memory cell and static random access memory cell |
| 09/12/2000 | US6117720 Method of making an integrated circuit electrode having a reduced contact area |
| 09/12/2000 | US6117719 Oxide spacers as solid sources for gallium dopant introduction |
| 09/12/2000 | US6117718 Method for forming BJT via formulation of high voltage device in ULSI |
| 09/12/2000 | US6117717 Method for after gate implant of threshold adjust with low impact on gate oxide integrity |
| 09/12/2000 | US6117716 Methods of forming BICMOS circuitry |
| 09/12/2000 | US6117715 Methods of fabricating integrated circuit field effect transistors by performing multiple implants prior to forming the gate insulating layer thereof |
| 09/12/2000 | US6117713 Method of producing a MESFET semiconductor device having a recessed gate structure |
| 09/12/2000 | US6117712 Method of forming ultra-short channel and elevated S/D MOSFETS with a metal gate on SOI substrate |
| 09/12/2000 | US6117711 Method of making single-electron-tunneling CMOS transistors |
| 09/12/2000 | US6117710 Plastic package with exposed die and method of making same |
| 09/12/2000 | US6117708 Encapsulant molding used in chip-on-board encapsulation wherein a hydrophobic, residual organic compound layer on the surface of carrier substrate is used to facilitate removal of unwanted encapsulant deposited during molding |
| 09/12/2000 | US6117707 Methods of producing integrated circuit devices |
| 09/12/2000 | US6117704 Stackable layers containing encapsulated chips |
| 09/12/2000 | US6117700 Method for fabricating semiconductor device having group III nitride |
| 09/12/2000 | US6117695 Apparatus and method for testing a flip chip integrated circuit package adhesive layer |
| 09/12/2000 | US6117694 Flexible lead structures and methods of making same |
| 09/12/2000 | US6117693 System for fabricating and testing assemblies containing wire bonded semiconductor dice |
| 09/12/2000 | US6117692 Calibrated methods of forming hemispherical grained silicon layers |
| 09/12/2000 | US6117691 Method of making a single transistor ferroelectric memory cell with asymmetrical ferroelectric polarization |
| 09/12/2000 | US6117690 Method of making thin, horizontal-plane hall sensors for read-heads in magnetic recording |
| 09/12/2000 | US6117689 Sputter depositing singl crystal platinum as oxygen barrier layer |
| 09/12/2000 | US6117688 Method for constructing ferroelectric based capacitor for use in memory systems |
| 09/12/2000 | US6117623 Remover solvent for partial removal of photoresist layer |