Patents
Sitemap › H01 - Basic electric elements › H01L - Semiconductor devices; Electric solid state devices not otherwise provided for › H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
Patents for H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof (658,974)
08/2000
08/01/2000US6096658 Semiconductor device having in-doped indium oxide etch stop
08/01/2000US6096657 Method for forming a spacer
08/01/2000US6096655 Method for forming vias and trenches in an insulation layer for a dual-damascene multilevel interconnection structure
08/01/2000US6096654 Gapfill of semiconductor structure using doped silicate glasses
08/01/2000US6096653 Method for fabricating conducting lines with a high topography height
08/01/2000US6096652 Method of chemical mechanical planarization using copper coordinating ligands
08/01/2000US6096651 Key-hole reduction during tungsten plug formation
08/01/2000US6096650 Treatment of a surface having exposed silica
08/01/2000US6096649 Creating dummy aluminum based structures to increase the roughens of the surface topography, improving adhesion between an overlying molding substance
08/01/2000US6096648 Copper/low dielectric interconnect formation with reduced electromigration
08/01/2000US6096647 Method to form CoSi2 on shallow junction by Si implantation
08/01/2000US6096646 Method for forming metal line of semiconductor device
08/01/2000US6096645 Stabilizing the vapor deposited titanium nitride films by treating with a high-power plasma for a prolonged duration to reduce the tendency of the resistance and thickness change
08/01/2000US6096644 Self-aligned contacts to source/drain silicon electrodes utilizing polysilicon and metal silicides
08/01/2000US6096643 Method of fabricating a semiconductor device having polysilicon line with extended silicide layer
08/01/2000US6096642 Method of forming self-aligned silicide in integrated circuit without causing bridging effects
08/01/2000US6096641 Method of manufacturing semiconductor device
08/01/2000US6096640 Method of making a gate electrode stack with a diffusion barrier
08/01/2000US6096639 Method of forming a local interconnect by conductive layer patterning
08/01/2000US6096638 Heating in an argon gas atmosphere to form a metal silicide interface between silicon surface and the first refractory metal layer which is covered by a nitrogen containing metal overcoatings
08/01/2000US6096637 Forming a multilayer interconnection intermetallics which are connected through plugs formed in a connecting hole
08/01/2000US6096636 Methods of forming conductive lines
08/01/2000US6096635 Method for creating via hole in chip
08/01/2000US6096634 Method of patterning a submicron semiconductor layer
08/01/2000US6096633 Dual damascene process for forming local interconnect
08/01/2000US6096632 Fabrication method of semiconductor device using CMP process
08/01/2000US6096631 Method of manufacturing semiconductor device
08/01/2000US6096630 Forming an amorphous metal silicide layer by injecting ions into the crystalline metal silicide layer, and heat treatment to form crystal structure
08/01/2000US6096629 Uniform sidewall profile etch method for forming low contact leakage schottky diode contact
08/01/2000US6096628 Method of controlling effective channel length of semiconductor device by non-doping implantation at elevated energies
08/01/2000US6096627 Method for introduction of an impurity dopant in SiC, a semiconductor device formed by the method and a use of a highly doped amorphous layer as a source for dopant diffusion into SiC
08/01/2000US6096626 Semiconductor structures and semiconductor processing methods of forming silicon layers
08/01/2000US6096625 Method for improved gate oxide integrity on bulk silicon
08/01/2000US6096624 Method for forming ETOX cell using self-aligned source etching process
08/01/2000US6096623 Method for forming shallow trench isolation structure
08/01/2000US6096622 Method of forming shallow trench isolation of semiconductor device
08/01/2000US6096621 Polysilicon filled trench isolation structure for soi integrated circuits
08/01/2000US6096620 Method of fabricating dynamic random access memory capacitor
08/01/2000US6096619 Method of manufacturing a semiconductor device comprising a capacitor with an intrinsic polysilicon electrode
08/01/2000US6096618 Method of making a Schottky diode with sub-minimum guard ring
08/01/2000US6096617 Preventing the formation of free atomic hydrogen by changing the first growth temperature to a second growth temperature under an alkylarsine
08/01/2000US6096616 Fabrication of a non-ldd graded p-channel mosfet
08/01/2000US6096615 Method of forming a semiconductor device having narrow gate electrode
08/01/2000US6096614 Method to fabricate deep sub-μm CMOSFETS
08/01/2000US6096613 Method for poly-buffered locos without pitting formation
08/01/2000US6096612 Increased effective transistor width using double sidewall spacers
08/01/2000US6096611 Method to fabricate dual threshold CMOS circuits
08/01/2000US6096609 ESD protection circuit and method for fabricating same using a plurality of dummy gate electrodes as a salicide mask for a drain
08/01/2000US6096608 Bidirectional trench gated power mosfet with submerged body bus extending underneath gate trench
08/01/2000US6096607 Method for manufacturing silicon carbide semiconductor device
08/01/2000US6096606 Method of making a semiconductor device
08/01/2000US6096605 Fabricating method of non-volatile flash memory device
08/01/2000US6096604 Production of reversed flash memory device
08/01/2000US6096603 Method of fabricating a split gate structure of a flash memory
08/01/2000US6096602 Method for fabricating flash memory cell
08/01/2000US6096601 Method of making a transistor and capacitor structure with a conductive pillar
08/01/2000US6096600 Method of forming a capacitative section of a semiconductor device and method of forming a capacitative section and gate section of a semiconductor device
08/01/2000US6096599 Formation of junctions by diffusion from a doped film into and through a silicide during silicidation
08/01/2000US6096598 Method for forming pillar memory cells and device formed thereby
08/01/2000US6096597 Improving dielectric material by annealing in oxygen plasma and then annealing in ozone plasma to reduce leakage current density
08/01/2000US6096596 Very high-density DRAM cell structure and method for fabricating it
08/01/2000US6096595 Integration of a salicide process for MOS logic devices, and a self-aligned contact process for MOS memory devices
08/01/2000US6096594 Fabricating method of a dynamic random access memory
08/01/2000US6096593 Method of fabricating capacitor of semiconductor device
08/01/2000US6096592 Methods of forming integrated circuit capacitors having plasma treated regions therein
08/01/2000US6096591 Method of making an IGFET and a protected resistor with reduced processing steps
08/01/2000US6096589 Low and high voltage CMOS devices and process for fabricating same
08/01/2000US6096588 Method of making transistor with selectively doped channel region for threshold voltage control
08/01/2000US6096587 Manufacturing method of a junction field effect transistor
08/01/2000US6096586 MOS device with self-compensating VaT -implants
08/01/2000US6096585 Method of manufacturing thin film transistor
08/01/2000US6096584 Silicon-on-insulator and CMOS-on-SOI double film fabrication process with a coplanar silicon and isolation layer and adding a second silicon layer on one region
08/01/2000US6096583 Semiconductor device and manufacturing method thereof
08/01/2000US6096582 Method of making a semiconductor device
08/01/2000US6096581 Method for operating an active matrix display device with limited variation in threshold voltages
08/01/2000US6096579 Method for controlling the thickness of a passivation layer on a semiconductor device
08/01/2000US6096578 Stress relief matrix for integrated circuit packaging
08/01/2000US6096577 Method of making semiconductor device, and film carrier tape
08/01/2000US6096576 Method of producing an electrical interface to an integrated circuit device having high density I/O count
08/01/2000US6096575 Optimum condition detection method for flip-chip
08/01/2000US6096574 Injecting a flowable liquid material between the spacings around the semiconductor chips and substrate, curing to form a compliant dielectric layer
08/01/2000US6096573 Method of manufacturing a CMOS sensor
08/01/2000US6096572 Forming an electrically conductive protection layer on metal layer to prevent oxidation of metal layer
08/01/2000US6096568 Process for preparing a semiconductor device package for analysis of a die
08/01/2000US6096567 Method and apparatus for direct probe sensing
08/01/2000US6096566 Inter-conductive layer fuse for integrated circuits
08/01/2000US6096565 Forming an interconnected layer by encasing within a noble metal gold or silver filled with the high temperature superconductor material; through-holes to enable direct connection of circuitry to the encased superconductor layer
08/01/2000US6096484 Pattern forming method using chemically amplified resist and apparatus for treating chemically amplified resist
08/01/2000US6096478 Resist comprises a resin for forming resist material, and given mixing ratio of first and second photo-acid generators of given molecular weights; the first produces an acid having a smaller diffusion length than the second; fewer defects
08/01/2000US6096462 Coulomb effect induced shifts in focal-point position, and changes in image magnification, projected-image rotation, and astigmatic blur and distortions are corrected by applying electric current supplied to correction lenses and stigmators
08/01/2000US6096460 Attenuating phase shift photomasks
08/01/2000US6096438 Aluminum alloy film has not only a low resistivity and high hillock resistance but also a high dielectric strength when it is anodized into an anodic oxide film
08/01/2000US6096434 The conductive oxide thin film is an epitaxial film composed of strontium ruthenate formed on silicon substrate
08/01/2000US6096433 Laminated substrate fabricated from semiconductor wafers bonded to each other without contact between insulating layer and semiconductor layer and process of fabrication thereof
08/01/2000US6096250 Covering and molding, electrodeposition of tape to form copper foil laminates
08/01/2000US6096233 Method for wet etching of thin film
08/01/2000US6096232 Dry etching system and dry etching method using plasma
08/01/2000US6096231 Chamber, at least for the transport of workpieces, a chamber combination, a vacuum treatment facility as well as a transport method
08/01/2000US6096230 Method of planarizing by polishing a structure which is formed to promote planarization
08/01/2000US6096176 Applying bias voltage to wafer while helicon wave plasma of high density generated between target and wafer by antenna
1 ... 5501 5502 5503 5504 5505 5506 5507 5508 5509 5510 5511 5512 5513 5514 5515 5516 5517 5518 5519 5520 5521 ... 6590