Patents
Sitemap › H01 - Basic electric elements › H01L - Semiconductor devices; Electric solid state devices not otherwise provided for › H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
Patents for H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof (658,974)
08/2000
08/08/2000US6100166 Process for producing semiconductor article
08/08/2000US6100165 Method of manufacturing semiconductor article
08/08/2000US6100164 Method of fabricating semiconductor device
08/08/2000US6100163 Gap filling of shallow trench isolation by ozone-tetraethoxysilane
08/08/2000US6100162 Method of forming a circuitry isolation region within a semiconductive wafer
08/08/2000US6100161 Method of fabrication of a raised source/drain transistor
08/08/2000US6100160 Oxide etch barrier formed by nitridation
08/08/2000US6100159 Quasi soi device
08/08/2000US6100158 Method of manufacturing an alignment mark with an etched back dielectric layer and a transparent dielectric layer and a device region on a higher plane with a wiring layer and an isolation region
08/08/2000US6100156 Method for forming a contact intermediate two adjacent electrical components
08/08/2000US6100155 Metal-oxide-metal capacitor for analog devices
08/08/2000US6100154 Using LPCVD silicon nitride cap as a barrier to reduce resistance variations from hydrogen intrusion of high-value polysilicon resistor
08/08/2000US6100153 Reliable diffusion resistor and diffusion capacitor
08/08/2000US6100152 Method of manufacturing a semiconductor device with a fast bipolar transistor
08/08/2000US6100151 Highly integrated bipolar junction transistors having trench-based emitter and base regions and methods of forming same
08/08/2000US6100150 Process to improve temperature uniformity during RTA by deposition of in situ poly on the wafer backside
08/08/2000US6100149 Method for rapid thermal processing (RTP) of silicon substrates
08/08/2000US6100148 Semiconductor device having a liner defining the depth of an active region, and fabrication thereof
08/08/2000US6100147 Method for manufacturing a high performance transistor with self-aligned dopant profile
08/08/2000US6100146 Method of forming trench transistor with insulative spacers
08/08/2000US6100145 Silicidation with silicon buffer layer and silicon spacers
08/08/2000US6100144 Semiconductor processing method of providing electrical isolation between adjacent semiconductor diffusion regions of different field effect transistors and integrated circuitry having adjacent electrically isolated field effect transistors
08/08/2000US6100143 Method of making a depleted poly-silicon edged MOSFET structure
08/08/2000US6100142 Method of fabricating sub-quarter-micron salicide polysilicon
08/08/2000US6100140 Manufacturing method of semiconductor device
08/08/2000US6100139 Method for producing semiconductor device
08/08/2000US6100138 Method to fabricate DRAM capacitor using damascene processes
08/08/2000US6100137 Etch stop layer used for the fabrication of an overlying crown shaped storage node structure
08/08/2000US6100136 Method of fabricating capacitor capable of maintaining the height of the peripheral area of the capacitor
08/08/2000US6100135 Method of forming a crown-fin shaped capacitor for a high density DRAM cell
08/08/2000US6100134 Method of fabricating semiconductor device
08/08/2000US6100133 Capacitors in integrated circuits
08/08/2000US6100132 Method of deforming a trench by a thermal treatment
08/08/2000US6100131 Method of fabricating a random access memory cell
08/08/2000US6100130 Method of manufacturing a semiconductor memory device having a trench capacitor
08/08/2000US6100129 Method for making fin-trench structured DRAM capacitor
08/08/2000US6100127 Self-aligned silicided MOS transistor with a lightly doped drain ballast resistor for ESD protection
08/08/2000US6100126 Method of making a resistor utilizing a polysilicon plug formed with a high aspect ratio
08/08/2000US6100124 Method for manufacturing a BiCMOS semiconductor device
08/08/2000US6100123 Pillar CMOS structure
08/08/2000US6100122 Thin film transistor having an insulating membrane layer on a portion of its active layer
08/08/2000US6100121 Method of fabricating a thin film transistor having a U-shaped gate electrode
08/08/2000US6100120 Method of locally forming a high-k dielectric gate insulator
08/08/2000US6100117 Method for manufacturing DRAM having a redundancy circuit region
08/08/2000US6100115 Semiconductor device
08/08/2000US6100114 Encapsulation of solder bumps and solder connections
08/08/2000US6100112 Method of manufacturing a tape carrier with bump
08/08/2000US6100111 Method for fabricating a silicon carbide device
08/08/2000US6100108 Method of fabricating electronic circuit device
08/08/2000US6100104 Method for fabricating a plurality of semiconductor bodies
08/08/2000US6100102 Method of in-line monitoring for shallow pit on semiconductor substrate
08/08/2000US6100100 Method for manufacturing capacitor element
08/08/2000US6100015 Resist pattern forming method
08/08/2000US6100013 Depositing hybrid resist on the substrate, exposing the resist through a mask, developing the resist, forming gate sidewall spacer in hybrid resist, etching through hybrid resist sidewall spacer, blanket exposure and development
08/08/2000US6100010 Forming a photoresist film on a layer to be etched, patterning the upper layer by applying light to which upper layer is sensitive, using mask, etching middle layer which has been exposed at patterning step, patterning lower layer
08/08/2000US6099992 Generating main pattern and first dummy patterns separated with spacings, dividing the dummy patterns into plurality of spaced apart second dummy patterns and measuring to find third pattern having specific value, connecting with second
08/08/2000US6099945 Atomic mask and method of patterning a substrate with the atomic mask
08/08/2000US6099939 Adhesion of metal by vapor depositon on substrate from organic dielectric layer
08/08/2000US6099935 Apparatus for providing solder interconnections to semiconductor and electronic packaging devices
08/08/2000US6099918 Method of preparing a poly-crystalline silicon film
08/08/2000US6099917 Pretreatment of oxide substrates and radiation reactive n2+ ion beams on oxide substrates
08/08/2000US6099904 Flowing a process gas comprising a tungsten-containing source, a group iii or v hydride and an additional reduction agent into said deposition zone, and stopping the flow of said hydride and increasing the pressure in said deposition zone
08/08/2000US6099803 Devices containing active electrodes especially adapted for electrophoretic transport of nucleic acids, their hybridization and analysis
08/08/2000US6099748 Silicon wafer etching method and silicon wafer etchant
08/08/2000US6099747 Grounding counter electrode and connecting substrate electrode to high frequence power source; introducing gas to form layer on wafer; chamber etching of apparatus; disconnecting from grounding and power; introducing fluorocarbon gas
08/08/2000US6099702 Electroplating chamber with rotatable wafer holder and pre-wetting and rinsing capability
08/08/2000US6099701 AlCu electromigration (EM) resistance
08/08/2000US6099697 Removing residual charges from the support surface of an electrostatic chuck
08/08/2000US6099687 Etching system
08/08/2000US6099686 Wet processing system
08/08/2000US6099681 Mounting apparatus for mounting small balls and mounting method thereof
08/08/2000US6099678 Laminating method of film-shaped organic die-bonding material, die-bonding method, laminating machine and die-bonding apparatus, semiconductor device, and fabrication process of semiconductor device
08/08/2000US6099677 Method of making microwave, multifunction modules using fluoropolymer composite substrates
08/08/2000US6099675 Resist removing method
08/08/2000US6099662 Process for cleaning a semiconductor substrate after chemical-mechanical polishing
08/08/2000US6099651 Temperature controlled chamber liner
08/08/2000US6099650 Structure and method for reducing slip in semiconductor wafers
08/08/2000US6099648 Domed wafer reactor vessel window with reduced stress at atmospheric and above atmospheric pressures
08/08/2000US6099647 Methods and apparatus for forming ultra-shallow doped regions using doped silicon oxide films
08/08/2000US6099645 Vertical semiconductor wafer carrier with slats
08/08/2000US6099643 Apparatus for processing a substrate providing an efficient arrangement and atmospheric isolation of chemical treatment section
08/08/2000US6099641 Apparatus for pulling a single crystal
08/08/2000US6099640 Molecular beam epitaxial growth method
08/08/2000US6099639 Method for solid-state formation of diamond
08/08/2000US6099604 Slurry with chelating agent for chemical-mechanical polishing of a semiconductor wafer and methods related thereto
08/08/2000US6099600 Method of making a vacuum-treated liquid electrolyte-filled flat electrolytic capacitor
08/08/2000US6099599 Multiple concentric ring sections circumferentially around a central hub area; each ring section has modular process units (mpus) each receiving with semiconductor device processing stations the size of shipping containers for easy repair
08/08/2000US6099598 Fabrication system and fabrication method
08/08/2000US6099597 Picker nest for holding an IC package with minimized stress on an IC component during testing
08/08/2000US6099596 Wafer out-of-pocket detection tool
08/08/2000US6099582 Automatic revision of semiconductor device layout for solving contradiction
08/08/2000US6099581 Layout database for a computer aided design system
08/08/2000US6099578 Method of estimating wire length including correction and summation of estimated wire length of every pin pair
08/08/2000US6099574 Method and apparatus for obtaining structure of semiconductor devices and memory for storing program for obtaining the same
08/08/2000US6099394 Polishing system having a multi-phase polishing substrate and methods relating thereto
08/08/2000US6099393 Polishing method for semiconductors and apparatus therefor
08/08/2000US6099390 Polishing pad for semiconductor wafer and method for polishing semiconductor wafer
08/08/2000US6099386 Control device for maintaining a chemical mechanical polishing machine in a wet mode
08/08/2000US6099302 Semiconductor wafer boat with reduced wafer contact area
08/08/2000US6099242 Wafer aligning apparatus for semiconductor device fabrication
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