Patents
Sitemap › H01 - Basic electric elements › H01L - Semiconductor devices; Electric solid state devices not otherwise provided for › H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
Patents for H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof (658,974)
08/2000
08/08/2000US6101371 Article comprising an inductor
08/08/2000US6101267 Position detecting method and apparatus, and exposure method and apparatus
08/08/2000US6101148 Dynamic random access memory
08/08/2000US6101140 Sense amplifier driver circuit for supplying a reduced driving voltage to sense amplifier
08/08/2000US6101131 Flash EEPROM device employing polysilicon sidewall spacer as an erase gate
08/08/2000US6101130 Semiconductor device memory cell and method for selectively erasing the same
08/08/2000US6101128 Nonvolatile semiconductor memory and driving method and fabrication method of the same
08/08/2000US6101124 Memory block for realizing semiconductor memory devices and corresponding manufacturing process
08/08/2000US6101123 Nonvolatile semiconductor memory with programming and erasing verification
08/08/2000US6101120 Semiconductor memory device
08/08/2000US6101117 Two transistor single capacitor ferroelectric memory
08/08/2000US6101098 Structure and method for mounting an electric part
08/08/2000US6101085 High dielectric constant thin film structure, method for forming high dielectric constant thin film, and apparatus for forming high dielectric constant thin film
08/08/2000US6101077 Electrostatic protection circuit of a semiconductor device
08/08/2000US6100987 Position detecting apparatus
08/08/2000US6100985 Method and apparatus for measurements of patterned structures
08/08/2000US6100977 Device and process for measuring two opposite surfaces of a body
08/08/2000US6100954 Liquid crystal display with planarizing organic gate insulator and organic planarization layer and method for manufacturing
08/08/2000US6100950 Active matrix LCD with thin film transistor switches and method of producing the same
08/08/2000US6100947 Liquid crystal panel substrate, liquid crystal panel and electronic apparatus using the same
08/08/2000US6100754 VT reference voltage for extremely low power supply
08/08/2000US6100748 Redundant circuit for semiconductor device having a controllable high voltage generator
08/08/2000US6100708 Probe card and wafer testing method using the same
08/08/2000US6100598 Sealed semiconductor device with positional deviation between upper and lower molds
08/08/2000US6100597 Semiconductor device and method for manufacturing the same
08/08/2000US6100594 Semiconductor device and method of manufacturing the same
08/08/2000US6100593 Multiple chip hybrid package using bump technology
08/08/2000US6100592 Integrated circuitry and method of forming a contact landing pad
08/08/2000US6100591 Semiconductor device and method of fabricating the same
08/08/2000US6100589 Semiconductor device and a method for making the same that provide arrangement of a connecting region for an external connecting terminal
08/08/2000US6100588 Multiple level conductor wordline strapping scheme
08/08/2000US6100587 Silicon carbide barrier layers for porous low dielectric constant materials
08/08/2000US6100581 Semiconductor chip packaging having printed circuitry or printed circuit registration feature
08/08/2000US6100580 Semiconductor device having all outer leads extending from one side of a resin member
08/08/2000US6100579 Insulating film for use in semiconductor device
08/08/2000US6100577 Contact process using Y-contact etching
08/08/2000US6100575 Semiconductor switching device having different carrier lifetimes between a first portion serving as a main current path and the remaining portion of the device
08/08/2000US6100574 Capacitors in integrated circuits
08/08/2000US6100571 Fet having non-overlapping field control electrode between gate and drain
08/08/2000US6100570 Semiconductor device having a semiconductor film of low oxygen concentration
08/08/2000US6100569 Semiconductor device with shared contact
08/08/2000US6100568 Semiconductor device including a memory cell and peripheral portion and method for forming same
08/08/2000US6100566 Multi-layer semiconductor device and method for fabricating the same
08/08/2000US6100565 Semiconductor integrated circuit device with operation in partial depletion type mode and perfect depletion type mode
08/08/2000US6100564 SOI pass-gate disturb solution
08/08/2000US6100563 Semiconductor device formed on SOI substrate
08/08/2000US6100562 Method of manufacturing a semiconductor device
08/08/2000US6100561 Method for forming LDD CMOS using double spacers and large-tilt-angle ion implantation
08/08/2000US6100559 Multipurpose graded silicon oxynitride cap layer
08/08/2000US6100558 Semiconductor device having enhanced gate capacitance by using both high and low dielectric materials
08/08/2000US6100556 Method of forming a semiconductor image sensor and structure
08/08/2000US6100555 Semiconductor device having a photosensitive organic film, and process for producing the same
08/08/2000US6100554 High-frequency semiconductor device
08/08/2000US6100550 Circuit cell based semiconductor integrated circuit device and method of arrangement-interconnection therefor
08/08/2000US6100549 High breakdown voltage resurf HFET
08/08/2000US6100548 Modulation-doped field-effect transistors and fabrication processes
08/08/2000US6100547 Field effect type semiconductor device and method of fabricating the same
08/08/2000US6100542 The electron supply layer includes a doped superlattice layer which includes two dissimilar layers of indium aluminum arsenide which alternates with each other for generating a two-dimentional electron gas
08/08/2000US6100536 Electron flood apparatus for neutralizing charge build-up on a substrate during ion implantation
08/08/2000US6100511 Method of bonding insulating wire and device for carrying out this method
08/08/2000US6100506 Hot plate with in situ surface temperature adjustment
08/08/2000US6100505 Hotplate offset ring
08/08/2000US6100475 Solder bonding printed circuit boards
08/08/2000US6100466 Method of forming microcrystalline silicon film, photovoltaic element, and method of producing same
08/08/2000US6100205 Intermetal dielectric layer formation with low dielectric constant using high density plasma chemical vapor deposition process
08/08/2000US6100204 Forming a gate electrode on a dielectric layer of an aluminum oxide made by exposing the substrate to aluminum chloride and oxygen; forming first/second source/drain regions in the substrate separated to define a channel; transistors
08/08/2000US6100203 Cleaning the exposed area of an electrode mask of silicon dioxide without excessive loss of capacitor area and hemispherically-shaped grained film using 0.01-10%, 1-10% hydrogen peroxide and .01-30% isopropyl alcohol
08/08/2000US6100202 First flowing a silicon source material absent a flow of a dopant source material; then depositing a doped silicate glass dielectric layer using chemical vapor deposition; anisotropically patterning a via with voidless sidewalls
08/08/2000US6100201 Method of forming a semiconductor memory device
08/08/2000US6100200 Sputtering process for the conformal deposition of a metallization or insulating layer
08/08/2000US6100199 Embedded thermal conductors for semiconductor chips
08/08/2000US6100198 Post-planarization, pre-oxide removal ozone treatment
08/08/2000US6100197 Method of fabricating a semiconductor device
08/08/2000US6100196 Method of making a copper interconnect with top barrier layer
08/08/2000US6100195 Passivation of copper interconnect surfaces with a passivating metal layer
08/08/2000US6100194 Silver metallization by damascene method
08/08/2000US6100193 Method of manufacturing a semiconductor device
08/08/2000US6100192 Method of forming high integrity tungsten silicide thin films
08/08/2000US6100191 Method for forming self-aligned silicide layers on sub-quarter micron VLSI circuits
08/08/2000US6100190 Method of fabricating semiconductor device, and semiconductor device
08/08/2000US6100189 Second implant for agglomeration control
08/08/2000US6100188 Stable and low resistance metal/barrier/silicon stack structure and related process for manufacturing
08/08/2000US6100187 Method of producing a barrier layer in a semiconductor body
08/08/2000US6100186 Method of selectively forming a contact in a contact hole
08/08/2000US6100185 Semiconductor processing method of forming a high purity <200> grain orientation tin layer and semiconductor processing method of forming a conductive interconnect line
08/08/2000US6100184 Method of making a dual damascene interconnect structure using low dielectric constant material for an inter-level dielectric layer
08/08/2000US6100183 Method for fabricating a via
08/08/2000US6100182 Method for forming metal interconnection of semiconductor device
08/08/2000US6100181 Low dielectric constant coating of conductive material in a damascene process for semiconductors
08/08/2000US6100180 Formation of a self-aligned integrated circuit structure using planarization to form a top surface
08/08/2000US6100177 Grooved wiring structure in semiconductor device and method for forming the same
08/08/2000US6100175 Method and apparatus for aligning and attaching balls to a substrate
08/08/2000US6100174 GaN group compound semiconductor device and method for producing the same
08/08/2000US6100173 Forming a self-aligned silicide gate conductor to a greater thickness than junction silicide structures using a dual-salicidation process
08/08/2000US6100172 Method for forming a horizontal surface spacer and devices formed thereby
08/08/2000US6100171 Reduction of boron penetration by laser anneal removal of fluorine
08/08/2000US6100170 Method of manufacturing semiconductor device
08/08/2000US6100169 Methods of fabricating silicon carbide power devices by controlled annealing
08/08/2000US6100168 Location selective transmutation doping on silicon wafers using high energy deuterons
08/08/2000US6100167 Process for the removal of copper from polished boron doped silicon wafers
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