Patents
Patents for H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof (658,974)
08/2000
08/02/2000EP1023641A1 Design rule checking system and method
08/02/2000EP1023639A1 Method and apparatus for data hierarchy maintenance in a system for mask description
08/02/2000EP1023582A1 Improved sample inspection system
08/02/2000EP1023469A1 Method of making a structure with improved material properties by moderate heat treatment of a metal deposit
08/02/2000EP1023139A1 Quality control method
08/02/2000EP0454051B1 Program element for use in redundancy technique for semiconductor memory device, and method of fabricating a semiconductor memory device having the same
08/02/2000CN1261984A Bipolar power transistor and manufacturing method
08/02/2000CN1261928A Low defect density silicon
08/02/2000CN1261727A Semiconductor device and its producing method
08/02/2000CN1261726A Oxide of nitrogen grid medium and its making method
08/02/2000CN1261725A Method for cleaning polymer after reaction ion eching on aluminium/copper metal connection wire
08/02/2000CN1261724A Connector with prolonged electric migration life
08/02/2000CN1261723A Method and device for preventing black silicon formation on edge of chip
08/02/2000CN1261568A Ultrasonic vibrative cutting method and its device
08/01/2000US6098024 System for process data association using LaPlace Everett interpolation
08/01/2000US6098023 Driving control system and monitoring device for fan filter unit in semiconductor clean room
08/01/2000US6097992 Method and controlling system for preventing the scratching of wafer backs by the fetch arm of a stepper machine
08/01/2000US6097790 Pressure partition for X-ray exposure apparatus
08/01/2000US6097666 Nonvolatile semiconductor memory device whose addresses are selected in a multiple access
08/01/2000US6097660 Semiconductor memory device
08/01/2000US6097654 Semiconductor memory
08/01/2000US6097652 Integrated circuit memory devices including circuits and methods for discharging isolation control lines into a reference voltage
08/01/2000US6097648 Semiconductor memory device having plurality of equalizer control line drivers
08/01/2000US6097642 Bus-line midpoint holding circuit for high speed memory read operation
08/01/2000US6097641 High performance DRAM structure employing multiple thickness gate oxide
08/01/2000US6097634 Latch-type sensing circuit and program-verify circuit
08/01/2000US6097626 MRAM device using magnetic field bias to suppress inadvertent switching of half-selected memory cells
08/01/2000US6097622 Ferroelectric memory used for the RFID system, method for driving the same, semiconductor chip and ID card
08/01/2000US6097621 Memory cell array architecture for random access memory device
08/01/2000US6097620 Multi-value dynamic semiconductor memory device having twisted bit line pairs
08/01/2000US6097610 Semiconductor device and method of manufacturing the same, circuit board, and electronic instrument
08/01/2000US6097492 Wafer detection apparatus
08/01/2000US6097483 Image detection apparatus
08/01/2000US6097474 Dynamically adjustable high resolution adjustable slit
08/01/2000US6097473 Exposure apparatus and positioning method
08/01/2000US6097469 Method of processing resist onto substrate and resist processing apparatus
08/01/2000US6097254 Output power amplifier circuit with short-circuit protective function
08/01/2000US6097205 Method and apparatus for characterizing a specimen of semiconductor material
08/01/2000US6097204 Inspection apparatus with real time display
08/01/2000US6097203 Integrated or intrapackage capability for testing electrical continuity between an integrated circuit and other circuitry
08/01/2000US6097114 Compact planar motor having multiple degrees of freedom
08/01/2000US6097113 MOS integrated circuit device operating with low power consumption
08/01/2000US6097103 Semiconductor device having an improved interconnection and method for fabricating the same
08/01/2000US6097102 Reticle, semiconductor wafer, and semiconductor chip
08/01/2000US6097099 Electro-thermal nested die-attach design
08/01/2000US6097097 Semiconductor device face-down bonded with pillars
08/01/2000US6097096 Metal attachment method and structure for attaching substrates at low temperatures
08/01/2000US6097095 Advanced fabrication method of integrated circuits with borderless vias and low dielectric-constant inter-metal dielectrics
08/01/2000US6097094 Semiconductor device having wiring layers and method of fabricating the same
08/01/2000US6097093 Structure of a dual damascene
08/01/2000US6097092 Freestanding multilayer IC wiring structure
08/01/2000US6097091 Semiconductor apparatus having an insulating layer of varying height therein
08/01/2000US6097090 High integrity vias
08/01/2000US6097089 Semiconductor plastic package, metal plate for said package, and method of producing copper-clad board for said package
08/01/2000US6097085 Electronic device and semiconductor package
08/01/2000US6097083 Semiconductor device which is crack resistant
08/01/2000US6097082 Semiconductor device
08/01/2000US6097081 Semiconductor device having adhesive between lead and chip
08/01/2000US6097079 Boron implanted dielectric structure
08/01/2000US6097078 Method for forming triple well in semiconductor device
08/01/2000US6097076 Self-aligned isolation trench
08/01/2000US6097072 Trench isolation with suppressed parasitic edge transistors
08/01/2000US6097070 MOSFET structure and process for low gate induced drain leakage (GILD)
08/01/2000US6097069 Method and structure for increasing the threshold voltage of a corner device
08/01/2000US6097068 Semiconductor device fabrication method and apparatus using connecting implants
08/01/2000US6097067 Semiconductor device with electrically isolated transistor
08/01/2000US6097062 Optimized trench edge formation integrated with high quality gate formation
08/01/2000US6097061 Trenched gate metal oxide semiconductor device and method
08/01/2000US6097060 Insulated gate semiconductor device
08/01/2000US6097059 Transistor, transistor array, method for manufacturing transistor array, and nonvolatile semiconductor memory
08/01/2000US6097058 Ferroelectric memory device and a method of manufacturing thereof
08/01/2000US6097057 Memory cell for EEPROM devices, and corresponding fabricating process
08/01/2000US6097056 Field effect transistor having a floating gate
08/01/2000US6097055 Capacitor and method for fabricating the same
08/01/2000US6097054 Semiconductor memory device and method of manufacturing the same
08/01/2000US6097053 Semiconductor device having a multi-wall cylindrical capacitor
08/01/2000US6097052 Semiconductor device and a method of manufacturing thereof
08/01/2000US6097051 Semiconductor device and method of fabricating
08/01/2000US6097050 Memory configuration with self-aligning non-integrated capacitor configuration
08/01/2000US6097049 DRAM cell arrangement
08/01/2000US6097047 Ferroelectric semiconductor device, and ferroelectric semiconductor substrate
08/01/2000US6097046 Vertical field effect transistor and diode
08/01/2000US6097045 Semiconductor device having discharging portion
08/01/2000US6097044 Charge transfer device and method for manufacturing the same
08/01/2000US6097043 Semiconductor integrated circuit and supply method for supplying multiple supply voltages in a semiconductor integrated circuit
08/01/2000US6097042 Symmetrical multi-layer metal logic array employing single gate connection pad region transistors
08/01/2000US6097039 Silicon carbide semiconductor configuration with a high degree of channel mobility
08/01/2000US6097038 Semiconductor device utilizing annealed semiconductor layer as channel region
08/01/2000US6097037 Thin film transistor having a continuous crystallized layer including the channel and portions of source and drain regions
08/01/2000US6097005 Substrate processing apparatus and substrate processing method
08/01/2000US6096981 Packaging electrical circuits
08/01/2000US6096913 Suppressing formation of a second metal-ligand complex of the metal with a higher valence by adding the elemental form of the metal to the synthesis of the first metal-ligand complex.
08/01/2000US6096848 Prepared by reacting 2-cyanoacrylic acids or their alkyl esters with diols in the presence of sulfonic acids as catalysts; adhesives for use in electronics
08/01/2000US6096808 Snap cure adhesive based on anhydride/epoxy resins
08/01/2000US6096664 Obtaining different gate oxide thickness by forming an inorganic layer over two silicon dioxide areas and exposed silicon surface; masking; growing another silicon dioxide layer on silicon substrate; removing mask
08/01/2000US6096663 Patterning a silicon nitride layer formed on a polysilicon layer to make segments spaced apart in the lateral direction having openings between of varying width; oxidizing the exposed polysilicon of varying thickness; doping
08/01/2000US6096662 NH3 /N2 plasma treatment to enhance the adhesion of silicon nitride to thermal oxide
08/01/2000US6096661 Method for depositing silicon dioxide using low temperatures
08/01/2000US6096660 Method for removing undesirable second oxide while minimally affecting a desirable first oxide
08/01/2000US6096659 Manufacturing process for reducing feature dimensions in a semiconductor