Patents
Sitemap › H01 - Basic electric elements › H01L - Semiconductor devices; Electric solid state devices not otherwise provided for › H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
Patents for H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof (658,974)
08/2000
08/15/2000US6104062 Semiconductor device having reduced effective substrate resistivity and associated methods
08/15/2000US6104061 Memory cell with vertical transistor and buried word and body lines
08/15/2000US6104060 Cost savings for manufacturing planar MOSFET devices achieved by implementing an improved device structure and fabrication process eliminating passivation layer and/or field plate
08/15/2000US6104059 Non-volatile memory having a silicide film on memory control gates and peripheral circuit transistor gates
08/15/2000US6104058 Method for improving the intermediate dielectric profile, particularly for non-volatile memories
08/15/2000US6104056 Semiconductor element and semiconductor memory device using the same
08/15/2000US6104055 Semiconductor device with memory cell having a storage capacitor with a plurality of concentric storage electrodes formed in an insulating layer and fabrication method thereof
08/15/2000US6104054 Space-efficient layout method to reduce the effect of substrate capacitance in dielectrically isolated process technologies
08/15/2000US6104053 Semiconductor device comprising capacitor in logic circuit area and method of fabricating the same
08/15/2000US6104052 Semiconductor device adopting a self-aligned contact structure and method for manufacturing a semiconductor memory device
08/15/2000US6104050 Methods for fabricating integrated circuit devices including etching barrier layers and related structures
08/15/2000US6104049 Ferroelectric memory with ferroelectric thin film having thickness of 90 nanometers or less, and method of making same
08/15/2000US6104044 Semiconductor compound electrode material containing calcium and a noble metal
08/15/2000US6104043 Schottky diode of SiC and a method for production thereof
08/15/2000US6104042 Thin film transistor with a multi-metal structure a method of manufacturing the same
08/15/2000US6104039 P-type nitrogen compound semiconductor and method of manufacturing same
08/15/2000US6104025 Ion implanting apparatus capable of preventing discharge flaw production on reverse side surface of wafer
08/15/2000US6104002 Heat treating apparatus
08/15/2000US6103992 Multiple frequency processing to minimize manufacturing variability of high aspect ratio micro through-vias
08/15/2000US6103991 Laser machining apparatus
08/15/2000US6103845 Norbornane-containing acrylic terpolymers
08/15/2000US6103680 Non-corrosive cleaning composition and method for removing photoresist and/or plasma etching residues
08/15/2000US6103639 Pretreatment of wafer surface bearing dielectric layer patterned with metal interconnects to strip any organic residue using ammonia and nitrous oxide plasma, then depositing silicon oxide buffer layer and silicon nitride
08/15/2000US6103638 Formation of planar dielectric layers using liquid interfaces
08/15/2000US6103637 Method for selective etching of antireflective coatings
08/15/2000US6103636 Method and apparatus for selective removal of material from wafer alignment marks
08/15/2000US6103635 Trench forming process and integrated circuit device including a trench
08/15/2000US6103634 Selectively etching away antireflective coating by reaction with fluorine precursor gas after removal of photoresist by different etchant
08/15/2000US6103633 Method for cleaning metal precipitates in semiconductor processes
08/15/2000US6103632 In situ Etching of inorganic dielectric anti-reflective coating from a substrate
08/15/2000US6103631 Method of manufacturing semiconductor device
08/15/2000US6103630 Adding SF6 gas to improve metal undercut for hardmask metal etching
08/15/2000US6103629 Self-aligned interconnect using high selectivity metal pillars and a via exclusion mask
08/15/2000US6103628 Reverse linear polisher with loadable housing
08/15/2000US6103627 Treatment of a surface having an exposed silicon/silica interface
08/15/2000US6103626 Method for forming dummy pattern areas in a semiconductor device
08/15/2000US6103625 Use of a polish stop layer in the formation of metal structures
08/15/2000US6103624 Method of improving Cu damascene interconnect reliability by laser anneal before barrier polish
08/15/2000US6103623 Method for fabricating a tungsten plug structure and an overlying interconnect metal structure without a tungsten etch back or CMP procedure
08/15/2000US6103622 Silicide process for mixed mode product with dual layer capacitor and polysilicon resistor which is protected with a capacitor protective oxide during silicidation of FET device
08/15/2000US6103621 Silicide process for mixed mode product with dual layer capacitor which is protected by a capacitor protective oxide during silicidation of FET device
08/15/2000US6103620 Method for producing titanium silicide
08/15/2000US6103619 Method of forming a dual damascene structure on a semiconductor wafer
08/15/2000US6103618 Method for forming an interconnection in a semiconductor element
08/15/2000US6103617 Fabricating method of multi-level wiring structure for semiconductor device
08/15/2000US6103616 Method to manufacture dual damascene structures by utilizing short resist spacers
08/15/2000US6103614 Alloying palladium-germanide with hydrogen during vapor deposition in 100 percent hydrogen ambient
08/15/2000US6103613 Method for fabricating semiconductor components with high aspect ratio features
08/15/2000US6103612 Isolated interconnect studs and method for forming the same
08/15/2000US6103611 Methods and arrangements for improved spacer formation within a semiconductor device
08/15/2000US6103610 Integrated circuit structure with dual thickness cobalt silicide layers and method for its manufacture
08/15/2000US6103609 Method for fabricating semiconductor device
08/15/2000US6103608 Method of forming a contact window
08/15/2000US6103607 Manufacture of MOSFET devices
08/15/2000US6103606 Forming improved dynamic random access memory circuit by covering first tungsten silicide layer with silicon-rich second silicide layer prior to forming cap oxide layer to resist oxidation of interface between silicide and cap oxide
08/15/2000US6103605 Process for defining the width of silicon gates using spacers as an etch hard mask
08/15/2000US6103603 Multi-step dry-etching method that sequentially uses plasma etching and reactive ion etching process steps to form the pairs of adjacent, dopes polysilicon gate electrodes without over-etching the dielectric film
08/15/2000US6103602 Method and system for providing a drain side pocket implant
08/15/2000US6103601 Method and apparatus for improving film stability of halogen-doped silicon oxide films
08/15/2000US6103600 Method for forming ultrafine particles and/or ultrafine wire, and semiconductor device using ultrafine particles and/or ultrafine wire formed by the forming method
08/15/2000US6103599 Planarizing technique for multilayered substrates
08/15/2000US6103598 Process for producing semiconductor substrate
08/15/2000US6103597 Method of obtaining a thin film of semiconductor material
08/15/2000US6103596 Process for etching a silicon nitride hardmask mask with zero etch bias
08/15/2000US6103595 Assisted local oxidation of silicon
08/15/2000US6103594 Method to form shallow trench isolations
08/15/2000US6103593 Method and system for providing a contact on a semiconductor device
08/15/2000US6103592 Manufacturing self-aligned polysilicon fet devices isolated with maskless shallow trench isolation and gate conductor fill technology with active devices and dummy doped regions formed in mesas
08/15/2000US6103591 Semiconductor device with air gaps between interconnections and method of forming the same
08/15/2000US6103590 Masking areas of silicon substrate with protective coating of chemical vapor deposited silicon carbide prior to treating non-masked areas with hydrogen fluoride electrolyte
08/15/2000US6103589 High-voltage device substrate structure and method of fabrication
08/15/2000US6103588 Method of forming a contact hole in a semiconductor device
08/15/2000US6103587 Method for forming a stacked structure capacitor in a semiconductor device
08/15/2000US6103586 Method for making integrated circuit capacitor including anchored plugs
08/15/2000US6103585 Method of forming deep trench capacitors
08/15/2000US6103583 Method for producing quantization functional device
08/15/2000US6103582 Method to suppress boron penetration in P+ mosfets
08/15/2000US6103581 Method for producing shallow trench isolation structure
08/15/2000US6103580 Forming metal-oxide-semiconductor field effect transistor (mosfet) for miniaturized random access memory using a doped silicate glass layer to source ions for the counter-doped ultra-shallow channel of the mosfet
08/15/2000US6103579 Method of isolating a SRAM cell
08/15/2000US6103578 Method for forming high breakdown semiconductor device
08/15/2000US6103577 Method of manufacturing a flash memory structure
08/15/2000US6103576 Dielectric layer of a memory cell having a stacked oxide sidewall and method of fabricating same
08/15/2000US6103575 Method of forming a single poly cylindrical flash memory cell having high coupling ratio
08/15/2000US6103574 Method of manufacturing non-volatile semiconductor memory device having reduced electrical resistance of a source diffusion layer
08/15/2000US6103573 Processing techniques for making a dual floating gate EEPROM cell array
08/15/2000US6103572 Method of fabricating a semiconductor nonvolatile storage device
08/15/2000US6103571 Method for forming a DRAM capacitor having improved capacitance and device formed
08/15/2000US6103570 Method of forming capacitors having an amorphous electrically conductive layer
08/15/2000US6103569 Method for planarizing local interconnects
08/15/2000US6103568 Manufacturing method of cylindrical stacked electrode
08/15/2000US6103567 Method of fabricating dielectric layer
08/15/2000US6103566 Method for manufacturing semiconductor integrated circuit device having a titanium electrode
08/15/2000US6103565 Semiconductor processing methods of forming capacitors and conductive lines
08/15/2000US6103563 Nitride disposable spacer to reduce mask count in CMOS transistor formation
08/15/2000US6103562 Method of making semiconductor device with decreased channel width and constant threshold voltage
08/15/2000US6103561 Depletion mode MOS capacitor with patterned VT implants
08/15/2000US6103560 Process for manufacturing a semiconductor device
08/15/2000US6103559 Method of making disposable channel masking for both source/drain and LDD implant and subsequent gate fabrication
08/15/2000US6103558 Process for producing electrooptical apparatus and process for producing driving substrate for electrooptical apparatus
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