| Patents for H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof (658,974) |
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| 08/29/2000 | US6111291 MOS transistor with high voltage sustaining capability |
| 08/29/2000 | US6111290 Semiconductor device having high breakdown voltage and method of manufacturing the same |
| 08/29/2000 | US6111289 Semiconductor device |
| 08/29/2000 | US6111287 Semiconductor device allowing electrical writing and erasing of information and method of manufacturing the same |
| 08/29/2000 | US6111285 Boride barrier layers to protect cell dielectrics such as tantalum oxide, strontium titanium oxide, barium strontium titanate, lead zirconium titanate, strontium bismuth tantalate against diffusion |
| 08/29/2000 | US6111284 Ferroelectric thin-film device |
| 08/29/2000 | US6111283 Triple well structure |
| 08/29/2000 | US6111277 Semiconductor device as well as light emitting semiconductor device |
| 08/29/2000 | US6111273 Semiconductor device and its manufacturing method |
| 08/29/2000 | US6111267 First silicon layer, stressed silicon germanium layer and the second silicon layer are grown by selective epitaxy; ensures that the stressed layer grows without any defects in the active regions |
| 08/29/2000 | US6111225 Wafer processing apparatus with a processing vessel, upper and lower separately sealed heating vessels, and means for maintaining the vessels at predetermined pressures |
| 08/29/2000 | US6111220 Circuit and method for heating an adhesive to package or rework a semiconductor die |
| 08/29/2000 | US6111198 Duplex feedthrough and method therefor |
| 08/29/2000 | US6111191 Sheet is made from silicon on a setter material which supports the silicon material; setter material and silicon are subjected to a thermal profile all of which promote columnar growth |
| 08/29/2000 | US6111184 Interchangeable pickup, electric stringed instrument and system for an electric stringed musical instrument |
| 08/29/2000 | US6111124 Such as tris-(2,2,6,6-tetramethyl-3,5-heptanedionato) bismuth n,n,n'n'-tetramethylethylenediamine adduct; use as precursors for chemical vapor deposition of bismuth for ferroelectric thin film devices, chalcogenides, and thermoelectric films |
| 08/29/2000 | US6111005 For bonding high density, microcircuit electronic components to substrates |
| 08/29/2000 | US6110881 That remove etching residue from substrates; nucleophilic amine compound of given formula having oxidation and reduction potentials, alkanolamine(s), water, and stabilizing chelating agent that prevents resettling of residue |
| 08/29/2000 | US6110845 Oxygen ions of a high concentration are implanted into a silicon substrate to form a high-concentration oxygen implanted layer, heating the substrate to form oxide layer, then pluse laser annealing melts and recrystallizes substrate |
| 08/29/2000 | US6110844 Reduction of particle deposition on substrates using temperature gradient control |
| 08/29/2000 | US6110843 Etch back method for smoothing microbubble-generated defects in spin-on-glass interlayer dielectric |
| 08/29/2000 | US6110842 Method of forming multiple gate oxide thicknesses using high density plasma nitridation |
| 08/29/2000 | US6110841 Method for avoiding plasma damage |
| 08/29/2000 | US6110840 Method of passivating the surface of a Si substrate |
| 08/29/2000 | US6110839 Dissolving metallic silicon and/or silicon compounds in an alkaline solution and neutralizing metallic ions in the alkaline solution by reaction products of hydrogen and silicates generated by reacting silicon and alkali |
| 08/29/2000 | US6110838 Isotropic polysilicon plus nitride stripping |
| 08/29/2000 | US6110837 Method for forming a hard mask of half critical dimension |
| 08/29/2000 | US6110836 Reactive plasma etch cleaning of high aspect ratio openings |
| 08/29/2000 | US6110835 Method for fabricating an electrode structure for a cylindrical capacitor in integrated circuit |
| 08/29/2000 | US6110834 Applying resist pattern to silicon-type semiconductor sample, performing dry etching on sample by using a reactive gas, and removing reaction products adhering to sample using sulfuric and hydrofluoric acids |
| 08/29/2000 | US6110833 Elimination of oxynitride (ONO) etch residue and polysilicon stringers through isolation of floating gates on adjacent bitlines by polysilicon oxidation |
| 08/29/2000 | US6110832 Dispensing a high viscosity slurry onto a rotating polishing pad and pressing the wafer onto the slurry coated polishing pad |
| 08/29/2000 | US6110831 Method of mechanical polishing |
| 08/29/2000 | US6110830 Forming aluminum-comprising layer over a substrate, polishing by contacting at least a portion of the aluminum-comprising layer with fluid, displacing the slurry with a second fluid comprising oxygen-containing oxidant |
| 08/29/2000 | US6110829 Ultra-low temperature Al fill for sub-0.25 μm generation of ICs using an Al-Ge-Cu alloy |
| 08/29/2000 | US6110828 In-situ capped aluminum plug (CAP) process using selective CVD AL for integrated plug/interconnect metallization |
| 08/29/2000 | US6110827 Planarization method for self-aligned contact process |
| 08/29/2000 | US6110826 Dual damascene process using selective W CVD |
| 08/29/2000 | US6110825 Process for forming front-back through contacts in micro-integrated electronic devices |
| 08/29/2000 | US6110823 Method of modifying the thickness of a plating on a member by creating a temperature gradient on the member, applications for employing such a method, and structures resulting from such a method |
| 08/29/2000 | US6110822 Method for forming a polysilicon-interconnect contact in a TFT-SRAM |
| 08/29/2000 | US6110821 Sputtering metal material from target while maintaining power to coil, shutting off power to target and passing gas through substrate support to backside, powering target and coil and passing gas to backside of substrate to heat to form silicide |
| 08/29/2000 | US6110820 Low scratch density chemical mechanical planarization process |
| 08/29/2000 | US6110818 Semiconductor device with gate electrodes for sub-micron applications and fabrication thereof |
| 08/29/2000 | US6110817 Method for improvement of electromigration of copper by carbon doping |
| 08/29/2000 | US6110816 Method for improving bondability for deep-submicron integrated circuit package |
| 08/29/2000 | US6110815 Electroplating fixture for high density substrates |
| 08/29/2000 | US6110814 Forming on substrate an insulating film containing phosphorus oxide by using film forming gas in which oxidizing gas is added to mixture including silicon compound and phosphorus compound, heating, fluidizing, planarizing |
| 08/29/2000 | US6110813 Forming insulator film on surface of silicon carbide, the film having opening through which surface of substrate is exposed, depositing metal film in opening, forming ohmic electrode of metal film by heating by irradiation with laser light |
| 08/29/2000 | US6110812 Method for forming polycide gate |
| 08/29/2000 | US6110811 Forming dielectric spacers on sidewalls of gate electrode, forming source and drain regions within semiconductor substrate adjacent to gate electrode, depositing layers of titanium over surfaces of semiconductor, annealing,stripping |
| 08/29/2000 | US6110810 Process for forming N-channel through amorphous silicon (αSi) implantation MOS process |
| 08/29/2000 | US6110809 Reacting first gas source containing an element of nitrogen with second gas containing a group iii metal trichloride and a carrier gas of hydrogen to form a group iii metal nitride |
| 08/29/2000 | US6110806 Process for precision alignment of chips for mounting on a substrate |
| 08/29/2000 | US6110805 Method and apparatus for attaching a workpiece to a workpiece support |
| 08/29/2000 | US6110803 Method for fabricating a high-bias device |
| 08/29/2000 | US6110802 Process for producing a structure with a low dislocation density comprising an oxide layer buried in a semiconductor substrate |
| 08/29/2000 | US6110801 Method of fabricating trench isolation for IC manufacture |
| 08/29/2000 | US6110800 Method for fabricating a trench isolation |
| 08/29/2000 | US6110799 Trench contact process |
| 08/29/2000 | US6110798 Method of fabricating an isolation structure on a semiconductor substrate |
| 08/29/2000 | US6110797 Process for fabricating trench isolation structure for integrated circuits |
| 08/29/2000 | US6110796 Method of improving junction leakage problem of shallow trench isolation by covering said STI with an insulating layer during salicide process |
| 08/29/2000 | US6110795 Method of fabricating shallow trench isolation |
| 08/29/2000 | US6110794 Semiconductor having self-aligned, buried etch stop for trench and manufacture thereof |
| 08/29/2000 | US6110793 Method for making a trench isolation having a conformal liner oxide and top and bottom rounded corners for integrated circuits |
| 08/29/2000 | US6110792 Method for making DRAM capacitor strap |
| 08/29/2000 | US6110791 Method of making a semiconductor variable capacitor |
| 08/29/2000 | US6110790 Method for making a MOSFET with self-aligned source and drain contacts including forming an oxide liner on the gate, forming nitride spacers on the liner, etching the liner, and forming contacts in the gaps |
| 08/29/2000 | US6110789 Contact formation using two anneal steps |
| 08/29/2000 | US6110788 Surface channel MOS transistors, methods for making the same, and semiconductor devices containing the same |
| 08/29/2000 | US6110787 Method for fabricating a MOS device |
| 08/29/2000 | US6110786 Semiconductor device having elevated gate electrode and elevated active regions and method of manufacture thereof |
| 08/29/2000 | US6110785 Formulation of high performance transistors using gate trim etch process |
| 08/29/2000 | US6110784 High dielectric constant and level of nitrogen doping |
| 08/29/2000 | US6110783 Method for forming a notched gate oxide asymmetric MOS device |
| 08/29/2000 | US6110782 Method to combine high voltage device and salicide process |
| 08/29/2000 | US6110781 Anisotropic chemical etching process of silicon oxide in the manufacture of MOS transistor flash EPROM devices |
| 08/29/2000 | US6110780 Using NO or N2 O treatment to generate different oxide thicknesses in one oxidation step for single poly non-volatile memory |
| 08/29/2000 | US6110779 Depositing a film containing silicon and nitrogen overlying polysilicon gate layer, forming resist mask pattern overlying film, exposing film, etching film based on the resist mask pattern, implanting exposed portion of film with impurity |
| 08/29/2000 | US6110777 Method of monitoring a process of manufacturing a semiconductor wafer including space hemispherical grain polysilicon |
| 08/29/2000 | US6110776 Method for forming bottom electrode of capacitor |
| 08/29/2000 | US6110775 Process for fabrication of a dram cell having a stacked capacitor |
| 08/29/2000 | US6110774 Method of forming a bit line over capacitor array of memory cells and an array of bit line over capacitor array of memory cells |
| 08/29/2000 | US6110773 Static random access memory device manufacturing method |
| 08/29/2000 | US6110772 Semiconductor integrated circuit and manufacturing method thereof |
| 08/29/2000 | US6110771 Fabrication method of a semiconductor device using self-aligned silicide CMOS having a dummy gate electrode |
| 08/29/2000 | US6110770 Semiconductor and process for fabricating the same |
| 08/29/2000 | US6110769 SOI (silicon on insulator) device and method for fabricating the same |
| 08/29/2000 | US6110768 Method of manufacturing aluminum gate electrode |
| 08/29/2000 | US6110767 Reversed MOS |
| 08/29/2000 | US6110766 Methods of fabricating aluminum gates by implanting ions to form composite layers |
| 08/29/2000 | US6110765 Semiconductor devices and assemblies |
| 08/29/2000 | US6110763 One mask, power semiconductor device fabrication process |
| 08/29/2000 | US6110761 Methods for simultaneously electrically and mechanically attaching lead frames to semiconductor dice and the resulting elements |
| 08/29/2000 | US6110760 Methods of forming electrically conductive interconnections and electrically interconnected substrates |
| 08/29/2000 | US6110759 Composite structure with a growth substrate having a diamond layer and a plurality of microelectronic components, and process for producing such a composite structure |
| 08/29/2000 | US6110757 Method of forming epitaxial wafer for light-emitting device including an active layer having a two-phase structure |
| 08/29/2000 | US6110755 Method for manufacturing semiconductor device |
| 08/29/2000 | US6110753 Bit lines have narrower widths and interval than wavelength of the exposure light without sacrificing the productivity; capable of avoiding the short circuit and the disconnection of the bit lines without sacrificing the productivity |