Patents
Sitemap › H01 - Basic electric elements › H01L - Semiconductor devices; Electric solid state devices not otherwise provided for › H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
Patents for H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof (658,974)
09/2000
09/19/2000US6121116 Flash memory device isolation method and structure
09/19/2000US6121115 Methods of fabricating integrated circuit memory devices having wide and narrow channel stop layers
09/19/2000US6121114 Method for preparing a dummy wafer
09/19/2000US6121113 Method for production of semiconductor device
09/19/2000US6121112 Fabrication method for semiconductor substrate
09/19/2000US6121111 Removing tungsten from edge of wafer after adjustment of dielectric material, forming apertures, coating, polishing, applying conductors and photoresists on wafers
09/19/2000US6121110 Trench isolation method for semiconductor device
09/19/2000US6121109 Method of forming hemispherical grain polysilicon over lower electrode capacitor
09/19/2000US6121108 Method for fabricating a capacitor in a dynamic random access memory
09/19/2000US6121107 Manufacturing process and structure of capacitor
09/19/2000US6121106 Method for forming an integrated trench capacitor
09/19/2000US6121105 Inverted thin film resistor and method of manufacture
09/19/2000US6121102 Method of electrical connection through an isolation trench to form trench-isolated bipolar devices
09/19/2000US6121101 Process for fabricating bipolar and BiCMOS devices
09/19/2000US6121100 Method of fabricating a MOS transistor with a raised source/drain extension
09/19/2000US6121099 Selective spacer formation for optimized silicon area reduction
09/19/2000US6121098 Semiconductor manufacturing method
09/19/2000US6121097 Semiconductor device manufacturing method
09/19/2000US6121096 Implant process utilizing as an implant mask, spacers projecting vertically beyond a patterned polysilicon gate layer
09/19/2000US6121095 Oxidation of silicon, forming gate oxide, adding nitrogen and annealing
09/19/2000US6121094 Substrates with dielectric layer over metal layer, oxygen layer, heat treatment of metal layer after oxygen impregnation, forming source/drain region
09/19/2000US6121093 Method of making asymmetrical transistor structures
09/19/2000US6121092 Silicide blocking process to form non-silicided regions on MOS devices
09/19/2000US6121091 Reduction of a hot carrier effect phenomena via use of transient enhanced diffusion processes
09/19/2000US6121090 Self-aligned silicided MOS devices with an extended S/D junction and an ESD protection circuit
09/19/2000US6121089 Methods of forming power semiconductor devices having merged split-well body regions therein
09/19/2000US6121088 Method of manufacture of undoped polysilicon as the floating-gate of a split-gate flash cell
09/19/2000US6121087 Integrated circuit device with embedded flash memory and method for manufacturing same
09/19/2000US6121086 Method of manufacturing a semiconductor integrated circuit device and a semiconductor integrated circuit device
09/19/2000US6121085 Method of fabricating contact openings for dynamic random-access memory
09/19/2000US6121084 Semiconductor processing methods of forming hemispherical grain polysilicon layers, methods of forming capacitors, and capacitors
09/19/2000US6121083 Fabrication of semiconductors from multilayer insulating films
09/19/2000US6121082 Construction of landing pads for dram cells
09/19/2000US6121081 Method to form hemi-spherical grain (HSG) silicon
09/19/2000US6121080 Electronic discharge protective circuit for DRAM
09/19/2000US6121079 Method for manufacturing a semiconductor memory device
09/19/2000US6121078 Integrated circuit planarization and fill biasing design method
09/19/2000US6121077 Silicon-on-insulator transistors having improved current characteristics and reduced electrostatic discharge susceptibility
09/19/2000US6121076 Method for producing semiconductor device
09/19/2000US6121075 Fabrication of two-dimensionally arrayed quantum device
09/19/2000US6121074 Fuse layout for improved fuse blow process window
09/19/2000US6121072 Method of fabricating nonvolatile memory device
09/19/2000US6121070 Flip chip down-bond: method and apparatus
09/19/2000US6121069 Connectors for integrated circuit chips with lead balls surrounded with barrier photoresists and tin coverings
09/19/2000US6121067 Method for additive de-marking of packaged integrated circuits and resulting packages
09/19/2000US6121064 STI fill for SOI which makes SOI inspectable
09/19/2000US6121062 Process of fabricating semiconductor unit employing bumps to bond two components
09/19/2000US6121061 Method of processing wafers with low mass support
09/19/2000US6121060 Method of measuring a concentration profile
09/19/2000US6121058 Method for removing accumulated solder from probe card probing features
09/19/2000US6120978 Surfactants and photoresists developers
09/19/2000US6120977 Photoresist with bleaching effect
09/19/2000US6120969 Phenolic resins for photoresists
09/19/2000US6120952 Achieving a desired transferred main feature dimension
09/19/2000US6120950 Optical element manufacturing method
09/19/2000US6120945 Method of developing a photoresist pattern and a developing apparatus
09/19/2000US6120917 Hybrid magnetic substrate and method for producing the same
09/19/2000US6120915 Integrated circuit with two silicon-containing structures over a metal layer having sidewalls which define a lateral space therebetween; silicon diffusion restriction structures between the silicon-containing structures and the sidewalls
09/19/2000US6120912 Thin film made by annealing an applied coating solution of metal alkoxides of bismuth, a specified metallic elements a and b respectively, which contains composite metal alkoxides formed by any two or more metal alkoxides
09/19/2000US6120846 Simultaneously exposing insulating portion and electrically conductive portion of substrate to chemical vapor deposition process; during procedure selectively depositing bismuth based ferroelectric thin film on electrically conductive portion
09/19/2000US6120844 Depositing self-aligning epsilon layer ofdeposition material on workpiece; depositing conducting material over epsilon layer
09/19/2000US6120842 Depositing porous thin film which predominantly comprises tin (titanium nitride); introducing aluminum into pores of porous thin film and onto surface which passivates porous thin film against atmospheric exposure
09/19/2000US6120834 Applying wet film to surface of substrate while substrate is held in place by support member; forming vacuum chamber around substrate while substrate is held in place by support member and while film is still wet; drying using vacuum
09/19/2000US6120749 Silicon single crystal with no crystal defect in peripheral part of wafer and process for producing the same
09/19/2000US6120697 Method of etching using hydrofluorocarbon compounds
09/19/2000US6120661 Apparatus for processing glass substrate
09/19/2000US6120641 Process architecture and manufacturing tool sets employing hard mask patterning for use in the manufacture of one or more metallization levels on a workpiece
09/19/2000US6120640 Etch resistant protective coating on aluminum substrate part
09/19/2000US6120610 Plasma etch system
09/19/2000US6120609 Self-aligning lift mechanism
09/19/2000US6120608 Workpiece support platen for semiconductor process chamber
09/19/2000US6120607 Apparatus and method for blocking the deposition of oxide on a wafer
09/19/2000US6120601 Wafer orientation inspection system
09/19/2000US6120599 Silicon single crystal wafer having few crystal defects, and method for producing the same
09/19/2000US6120597 Crystal ion-slicing of single-crystal films
09/19/2000US6120571 A polishing agent for semiconductor, comprising cerium oxide particles having a weight average particle size of from 0.2 to 0.3 mu.m, a crystallite size from 300 to 500 ang, and specific area of 15 to 30 m2/gram
09/19/2000US6120550 Design file templates for implementation of logic designs
09/19/2000US6120371 Docking and environmental purging system for integrated circuit wafer transport assemblies
09/19/2000US6120366 Chemical-mechanical polishing pad
09/19/2000US6120360 Apparatus for processing a planar structure
09/19/2000US6120354 Method of chemical mechanical polishing
09/19/2000US6120350 Process for reconditioning polishing pads
09/19/2000US6120348 Polishing system
09/19/2000US6120301 Semiconductor device and method of manufacturing the same
09/19/2000US6120229 Substrate carrier as batchloader
09/19/2000US6119926 Method for producing wire connections on semiconductor chips
09/19/2000US6119923 Packaging electrical circuits
09/19/2000US6119919 Method and device for repairing defective soldered joints
09/19/2000US6119917 Wire bonding apparatus and bonding load correction method for the same
09/19/2000US6119914 Wire bonding apparatus
09/19/2000US6119895 Method and apparatus for dispensing materials in a vacuum
09/19/2000US6119865 Accommodation container and accommodating method
09/19/2000US6119736 Vehicle for transporting wet objects
09/19/2000US6119709 Feeding apparatus and replenishing method of processing solution
09/19/2000US6119708 Method and apparatus for cleaning the edge of a thin disc
09/19/2000US6119675 Method for sawing wafers employing multiple indexing techniques for multiple die dimensions
09/19/2000US6119592 Apparatus for screen printing having a belt screen and locking frame
09/19/2000US6119532 Apparatus and method for particle sampling during semiconductor device manufacturing
09/19/2000US6119460 Temperature control system for test heads
09/19/2000US6119368 Apparatus for reducing cool chamber particles
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