Patents
Sitemap › H01 - Basic electric elements › H01L - Semiconductor devices; Electric solid state devices not otherwise provided for › H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
Patents for H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof (658,974)
09/2000
09/19/2000US6122177 Semiconductor device-mounted on a printed circuit board having solder bumps with excellent connection reliability
09/19/2000US6122159 Electrostatic holding apparatus
09/19/2000US6122107 Angular integrator
09/19/2000US6122059 Scanning exposure apparatus and device fabrication method in which multiple laser interferometers use a respective laser head
09/19/2000US6122056 Direct phase shift measurement between interference patterns using aerial image measurement tool
09/19/2000US6121950 Control system for display panels
09/19/2000US6121852 Distributed constant element using a magnetic thin film
09/19/2000US6121786 Semiconductor integrated circuit
09/19/2000US6121783 Method and apparatus for establishing electrical contact between a wafer and a chuck
09/19/2000US6121743 Dual robotic arm end effectors having independent yaw motion
09/19/2000US6121690 Semiconductor device having two pluralities of electrode pads, pads of different pluralities having different widths and respective pads of different pluralities having an aligned transverse edge
09/19/2000US6121689 Semiconductor flip-chip package and method for the fabrication thereof
09/19/2000US6121688 Anisotropic conductive sheet and printed circuit board
09/19/2000US6121687 Input-output circuit cell and semiconductor integrated circuit apparatus
09/19/2000US6121684 Integrated butt contact having a protective spacer
09/19/2000US6121683 Electronic device and integrated circuit
09/19/2000US6121682 Multi-chip package
09/19/2000US6121678 Wrap-around interconnect for fine pitch ball grid array
09/19/2000US6121677 Reduced size integrated circuits and methods using test pads located in scribe regions of integrated circuits wafers
09/19/2000US6121674 Die paddle clamping method for wire bond enhancement
09/19/2000US6121671 Semiconductor device having a substrate, an undoped silicon oxide structure, and an overlying doped silicon oxide structure with a side wall terminating at the undoped silicon oxide structure
09/19/2000US6121670 Single-chip contact-less read-only memory (ROM) device and the method for fabricating the device
09/19/2000US6121668 Semiconductor device provided with conductor electrically connected to conducting region
09/19/2000US6121666 Split gate oxide asymmetric MOS devices
09/19/2000US6121664 Semiconductor memory device
09/19/2000US6121663 Local interconnects for improved alignment tolerance and size reduction
09/19/2000US6121662 3-D CMOS transistors with high ESD reliability
09/19/2000US6121661 Silicon-on-insulator structure for electrostatic discharge protection and improved heat dissipation
09/19/2000US6121660 Channel etch type bottom gate semiconductor device
09/19/2000US6121659 Buried patterned conductor planes for semiconductor-on-insulator integrated circuit
09/19/2000US6121658 Deep mesa isolation
09/19/2000US6121656 Semiconductor memory device mounted with a light emitting device
09/19/2000US6121655 Nonvolatile semiconductor memory device and method for fabricating the same and semiconductor integrated circuit
09/19/2000US6121654 Memory device having a crested tunnel barrier
09/19/2000US6121653 Dram capacitor arrays with 3-capacitor and 6-capacitor geometries
09/19/2000US6121652 Semiconductor device including active matrix circuit
09/19/2000US6121651 Dram cell with three-sided-gate transfer device
09/19/2000US6121650 Semiconductor memory device with increased charge retention capacity and method for forming the same
09/19/2000US6121649 Semiconductor device with ferroelectric capacitors
09/19/2000US6121648 Ferroelectric based memory devices utilizing hydrogen getters and recovery annealing
09/19/2000US6121647 A perovskite crystalline lead, titanium and a rare earth oxide used in a semiconductor device, e.g., nonvolatile memories; infrared sensors; optical modulators, switches, integrated circuits; reduced leakage; reverse polarity
09/19/2000US6121645 Noise-reducing circuit
09/19/2000US6121644 Semiconductor integrated circuit device and method of arranging and wiring cells
09/19/2000US6121643 Semiconductor device having a group of high performance transistors and method of manufacture thereof
09/19/2000US6121642 Junction mott transition field effect transistor (JMTFET) and switch for logic and memory applications
09/19/2000US6121641 Compound semiconductor field-effect transistor with improved current flow characteristic
09/19/2000US6121633 Latch-up free power MOS-bipolar transistor
09/19/2000US6121632 Thin-film transistor array and method for manufacturing same
09/19/2000US6121631 Test structure to determine the effect of LDD length upon transistor performance
09/19/2000US6121625 Charged particle beam lithography apparatus for forming pattern on semi-conductor
09/19/2000US6121624 Method for controlled implantation of elements into the surface or near surface of a substrate
09/19/2000US6121581 Semiconductor processing system
09/19/2000US6121580 Lamp annealer and method for annealing semiconductor wafer
09/19/2000US6121579 Heating apparatus, and processing apparatus
09/19/2000US6121218 Contains alcohol; ether; organic acid, poly acid, acid anhydride, or acid halide; urea, thiourea or derivative thereof
09/19/2000US6121217 Removal of process residue from substrate of titanium (metal, alloy, or compound) with aqueous solution of alkanolamine, gallic acid or catechol chelating agent, hydroxylamine
09/19/2000US6121164 Method for forming low compressive stress fluorinated ozone/TEOS oxide film
09/19/2000US6121163 Forming a layer on substrates by vapor deposition
09/19/2000US6121162 Insulating film with fluorine and gas flow
09/19/2000US6121161 Reduction of mobile ion and metal contamination in HDP-CVD chambers using chamber seasoning film depositions
09/19/2000US6121160 Multilayer semiconductor of polyimides layers and insulator films
09/19/2000US6121159 Polymeric dielectric layers having low dielectric constants and improved adhesion to metal lines
09/19/2000US6121158 Method for hardening a photoresist material formed on a substrate
09/19/2000US6121157 Semiconductor device and its manufacture
09/19/2000US6121156 Contact monitor, method of forming same and method of analyzing contact-, via-and/or trench-forming processes in an integrated circuit
09/19/2000US6121155 Integrated circuit fabrication critical dimension control using self-limiting resist etch
09/19/2000US6121154 Etching multilayer nitride photoresists
09/19/2000US6121153 Semiconductors with crystallization and dopes of mixtures of gallium arsenide with aluminum or indium
09/19/2000US6121152 Method and apparatus for planarization of metallized semiconductor wafers using a bipolar electrode assembly
09/19/2000US6121150 Sputter-resistant hardmask for damascene trench/via formation
09/19/2000US6121149 Optimized trench/via profile for damascene filling
09/19/2000US6121148 Semiconductor device trench isolation structure with polysilicon bias voltage contact
09/19/2000US6121147 Apparatus and method of detecting a polishing endpoint layer of a semiconductor wafer which includes a metallic reporting substance
09/19/2000US6121146 Method for forming contact plugs of a semiconductor device
09/19/2000US6121145 Method of fabricating via and interconnection
09/19/2000US6121144 Low temperature chemical mechanical polishing of dielectric materials
09/19/2000US6121143 Abrasive articles comprising a fluorochemical agent for wafer surface modification
09/19/2000US6121141 Method of forming a void free copper interconnects
09/19/2000US6121139 Forming titanium silicide with sputtering, dielectrics and forming nitrides with nitrogen gas
09/19/2000US6121138 Collimated deposition of titanium onto a substantially vertical nitride spacer sidewall to prevent silicide bridging
09/19/2000US6121137 Forming a titanium film over silicon substrate, annealing to form silicide and single crystal silicon film, then diffusion
09/19/2000US6121136 Method of forming contact plug
09/19/2000US6121135 Modified buried contact process for IC device fabrication
09/19/2000US6121134 High aspect ratio metallization structures and processes for fabricating the same
09/19/2000US6121133 Isolation using an antireflective coating
09/19/2000US6121132 Method for reducing stress on collimator titanium nitride layer
09/19/2000US6121131 Substrate with surface metal hydrogen layer, metal layer and heat treatment
09/19/2000US6121130 Dielectric layers on substrates with curing
09/19/2000US6121129 Method of contact structure formation
09/19/2000US6121128 Method for making borderless wordline for DRAM cell
09/19/2000US6121127 Methods and devices related to electrodes for p-type group III nitride compound semiconductors
09/19/2000US6121126 Layers of silicon and germanium, oxidation and forming integrated circuits
09/19/2000US6121125 Method of forming polycide gate
09/19/2000US6121124 Process for fabricating integrated circuits with dual gate devices therein
09/19/2000US6121123 Gate pattern formation using a BARC as a hardmask
09/19/2000US6121121 Method for manufacturing gallium nitride compound semiconductor
09/19/2000US6121120 Method for manufacturing semiconductor device capable of flattening surface of selectively-grown silicon layer
09/19/2000US6121119 Resistor fabrication
09/19/2000US6121118 Chip separation device and method
09/19/2000US6121117 Process for producing semiconductor substrate by heat treating
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