| Patents for H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof (658,974) |
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| 09/26/2000 | US6124638 Semiconductor device and a method of manufacturing the same |
| 09/26/2000 | US6124634 Micromachined chip scale package |
| 09/26/2000 | US6124633 Vertical interconnect process for silicon segments with thermally conductive epoxy preform |
| 09/26/2000 | US6124629 Semiconductor device including a resin sealing member which exposes the rear surface of the sealed semiconductor chip |
| 09/26/2000 | US6124627 Lateral MOSFET having a barrier between the source/drain region and the channel region using a heterostructure raised source/drain region |
| 09/26/2000 | US6124626 Capacitor structures formed using excess oxygen containing material provided relative to electrodes thereof |
| 09/26/2000 | US6124624 Q inductor with multiple metallization levels |
| 09/26/2000 | US6124623 Semiconductor device having channel stop regions |
| 09/26/2000 | US6124622 MIS transistor with a three-layer device isolation film surrounding the MIS transistor |
| 09/26/2000 | US6124621 A semiconductor having a structure of a spacer for keeping the gate intact after solvent and ion implantation |
| 09/26/2000 | US6124620 Incorporating barrier atoms into a gate dielectric using gas cluster ion beam implantation |
| 09/26/2000 | US6124619 Semiconductor device including upper, lower and side oxidation-resistant films |
| 09/26/2000 | US6124617 Semiconductor device and method of fabricating same |
| 09/26/2000 | US6124616 Integrated circuitry comprising halo regions and LDD regions |
| 09/26/2000 | US6124614 Si/SiGe MOSFET and method for fabricating the same |
| 09/26/2000 | US6124613 SOI-MOS field effect transistor that withdraws excess carrier through a carrier path silicon layer |
| 09/26/2000 | US6124612 FET with source-substrate connection and method for producing the FET |
| 09/26/2000 | US6124611 Epitaxial channel vertical MOS transistor |
| 09/26/2000 | US6124610 Isotropically etching sidewall spacers to be used for both an NMOS source/drain implant and a PMOS LDD implant |
| 09/26/2000 | US6124609 Split gate flash memory with buried source to shrink cell dimension and increase coupling ratio |
| 09/26/2000 | US6124608 Non-volatile trench semiconductor device having a shallow drain region |
| 09/26/2000 | US6124607 Capacitive memory cell |
| 09/26/2000 | US6124606 Method of making a large area imager with improved signal-to-noise ratio |
| 09/26/2000 | US6124604 Liquid crystal display device provided with auxiliary circuitry for reducing electrical resistance |
| 09/26/2000 | US6124603 Complementary integrated circuit having N channel TFTs and P channel TFTs |
| 09/26/2000 | US6124602 Semiconductor circuit having a crystal growth in an active layer where a specific distance is established between a selected portion and where the growth starts to the active layer of the circuit |
| 09/26/2000 | US6124601 Position sensor having a reflective projecting system and device fabrication method using the sensor |
| 09/26/2000 | US6124599 Electron beam exposure system and method of manufacturing devices using the same |
| 09/26/2000 | US6124598 Pattern exposure method and system |
| 09/26/2000 | US6124547 Tape carrier package |
| 09/26/2000 | US6124427 Mixing a triorganometallic compound of aluminum with a triorganooxymetallic compound of said aluminum in a solvent to form a reaction mixture and decomposing to remove organic ligand foring aluminum oxide with aluminum:oxygen ratio 2:3 |
| 09/26/2000 | US6124405 Polymers for photoresist compositions |
| 09/26/2000 | US6124372 Improved photoresist compositions and improved thermal ink jet printheads |
| 09/26/2000 | US6124218 Providing semiconductor structures having impurity doped surfaces on a substrate, preparing a hydride gas containing the doping impurity as well as hydrogen, plasma-cleaning the impurity doped surfaces in a vacuum to remove native oxide |
| 09/26/2000 | US6124217 Forming a silicon oxynitride layer upon a semiconductor topography, perfomring a bake of silicon oxynitride layer, and forming an oxide layer directly over said silicon oxynitride layer thereby forming the interlevel dielectric |
| 09/26/2000 | US6124216 Forming a dielectric layer on said substrate, the dielectric layer including hydrogen bonded with at least one other element and removing the hydrogen bonding by heat treatment in ozone plasma to break hydrogen bond forming siliocn oxide |
| 09/26/2000 | US6124215 Enclosure surrounding the spin-on table and substrate and the application of a planarization pressure plate to the substrate, subsequent to dispersal of the spin-on materials and during rotation of the substrate, heating and curing |
| 09/26/2000 | US6124214 Method and apparatus for ultrasonic wet etching of silicon |
| 09/26/2000 | US6124213 Forming a semiconductor structure having a layer formed of a material to be damaged by an oxygen plasma, forming a photoresist mask, selectively etching the semiconductor structure to modify it, removing the mask with hydrazine |
| 09/26/2000 | US6124212 First and second plasma etching containing source of oxygen, source of nitrogen and source of bromine etchan to polysilicon layer forming pattern polysilicon while supressing micro-loading effect |
| 09/26/2000 | US6124211 Cleaning method |
| 09/26/2000 | US6124210 Oxidizing the particles present on the substrate by contacting a pre-process gas containing ozone to the surface of the substrate, and removing the particles by heating to exceed a decoposition point of oxide of the particles |
| 09/26/2000 | US6124209 Method for treating a surface of a silicon single crystal and a method for manufacturing a silicon single crystal thin film |
| 09/26/2000 | US6124208 Method of preventing bowing in a via formation process |
| 09/26/2000 | US6124207 Slurries for mechanical or chemical-mechanical planarization of microelectronic-device substrate assemblies, and methods and apparatuses for making and using such slurries |
| 09/26/2000 | US6124206 Reduced pad erosion |
| 09/26/2000 | US6124205 Filling contact holes with a low melting point aluminum alloy andsubsequently depositing a second layer dopant for diffusion into aluminum filled contact hole to form an alloy |
| 09/26/2000 | US6124204 Forming a dielectric layer over formed copper layer, forming a via hole to penetrate through the dielectric layer and expose a part of copper, exposed copper reacts with oxygen to form coppe oxide, removing it with hexafluoropentanedione |
| 09/26/2000 | US6124203 Method for forming conformal barrier layers |
| 09/26/2000 | US6124202 Forming a first silicide layer over conductive layer by reacting silane with tungsten hexafluoride in a ratio of 200:1 to 400:1, forming second silicide layer on first layer having lower concentration of silicon than first layer |
| 09/26/2000 | US6124201 Method for manufacturing semiconductors with self-aligning vias |
| 09/26/2000 | US6124200 Method of fabricating an unlanded via |
| 09/26/2000 | US6124199 Method for simultaneously forming a storage-capacitor electrode and interconnect |
| 09/26/2000 | US6124198 Ultra high-speed chip interconnect using free-space dielectrics |
| 09/26/2000 | US6124197 Adjusting the size of conductive lines based upon contact size |
| 09/26/2000 | US6124196 Variable circuit connector and method of fabricating the same |
| 09/26/2000 | US6124194 Method of fabrication of anti-fuse integrated with dual damascene process |
| 09/26/2000 | US6124193 Raised tungsten plug antifuse and fabrication processes |
| 09/26/2000 | US6124192 Method for fabricating ultra-small interconnections using simplified patterns and sidewall contact plugs |
| 09/26/2000 | US6124191 Self-aligned contact process using low density/low k dielectric |
| 09/26/2000 | US6124190 Method of manufacturing semiconductor device with silicide layer without short circuit |
| 09/26/2000 | US6124189 Metallization structure and method for a semiconductor device |
| 09/26/2000 | US6124188 Semiconductor device and fabrication method using a germanium sacrificial gate electrode plug |
| 09/26/2000 | US6124187 Method of fabricating semiconductor device |
| 09/26/2000 | US6124186 Flowing silicohydride gas on a filament to decompose the gas into silicon and hydrogen atoms, allowing product of gas reaction between both atomic species and silicon hydride to migrated and deposit on the substrate |
| 09/26/2000 | US6124185 Method for producing a semiconductor device using delamination |
| 09/26/2000 | US6124184 Method for forming isolation region of semiconductor device |
| 09/26/2000 | US6124183 Shallow trench isolation formation with simplified reverse planarization mask |
| 09/26/2000 | US6124182 Method of forming stacked capacitor |
| 09/26/2000 | US6124181 Method for manufacturing bipolar transistor capable of suppressing deterioration of transistor characteristics |
| 09/26/2000 | US6124180 BiCMOS process for counter doped collector |
| 09/26/2000 | US6124179 Inverted dielectric isolation process |
| 09/26/2000 | US6124178 Forming a non-doped silicate glass on doped semiconductor substrate to cover gate, sidewall, spacers, and doping areas, annealing the substrate to reduce structural stress between silicon oxynitride and glass layer and promoting adhesion |
| 09/26/2000 | US6124177 Method for making deep sub-micron mosfet structures having improved electrical characteristics |
| 09/26/2000 | US6124176 Method of producing a semiconductor device with reduced fringe capacitance and short channel effect |
| 09/26/2000 | US6124175 Rapid thermal anneal with a gaseous dopant species |
| 09/26/2000 | US6124174 Spacer structure as transistor gate |
| 09/26/2000 | US6124173 Method for improved storage node isolation |
| 09/26/2000 | US6124172 A gate electrode is formed over a substrate and a protective layer over gate electrode, selective removal of protective layer to expose a edge region, upper portion of peripheral region of gate is removed, then light and heavy doping |
| 09/26/2000 | US6124171 Forming first gate oxide film of first thicknes on a substrate, followed by a hydrogen balanced silicon nitride film over the oxide film, masking and etching both film to expose substrate area, growing oxide film of second thickness |
| 09/26/2000 | US6124170 Method for making flash memory |
| 09/26/2000 | US6124169 Contact structure and associated process for production of semiconductor electronic devices and in particular nonvolatile EPROM and flash EPROM memories |
| 09/26/2000 | US6124168 Method for forming an asymmetric floating gate overlap for improved device performance in buried bit-line devices |
| 09/26/2000 | US6124167 Method for forming an etch mask during the manufacture of a semiconductor device |
| 09/26/2000 | US6124166 Method of forming a lower electrode of a capacitor in a DRAM cell |
| 09/26/2000 | US6124165 Method for making openings in a passivation layer over polycide fuses using a single mask while forming reliable tungsten via plugs on DRAMs |
| 09/26/2000 | US6124164 Method of making integrated capacitor incorporating high K dielectric |
| 09/26/2000 | US6124163 Integrated chip multiplayer decoupling capacitors |
| 09/26/2000 | US6124162 Method for manufacturing cylindrical lower electrode of DRAM capacitor |
| 09/26/2000 | US6124161 Method for fabricating a hemispherical silicon grain layer |
| 09/26/2000 | US6124160 Semiconductor device and method for manufacturing the same |
| 09/26/2000 | US6124159 Method for integrating high-voltage device and low-voltage device |
| 09/26/2000 | US6124158 Method of reducing carbon contamination of a thin dielectric film by using gaseous organic precursors, inert gas, and ozone to react with carbon contaminants |
| 09/26/2000 | US6124157 Integrated non-volatile and random access memory and method of forming the same |
| 09/26/2000 | US6124156 Process for manufacturing a CMOS circuit with all-around dielectrically insulated source-drain regions |
| 09/26/2000 | US6124155 Electro-optical device and thin film transistor and method for forming the same |
| 09/26/2000 | US6124154 Fabrication process for thin film transistors in a display or electronic device |
| 09/26/2000 | US6124153 Method for manufacturing a polysilicon TFT with a variable thickness gate oxide |
| 09/26/2000 | US6124152 Method for fabricating cob type semiconductor package |
| 09/26/2000 | US6124151 Plastic lead frames for semiconductor devices, packages including same, and methods of fabrication |