Patents
Sitemap › H01 - Basic electric elements › H01L - Semiconductor devices; Electric solid state devices not otherwise provided for › H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
Patents for H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof (658,974)
11/2000
11/07/2000US6144057 Semiconductor memory device including a field effect transistor
11/07/2000US6144056 Methods of forming conductive lines, methods of forming insulative spacers over conductive line sidewalls, methods of forming memory circuitry, and memory circuitry
11/07/2000US6144055 Semiconductor memory device
11/07/2000US6144054 DRAM cell having an annular signal transfer region
11/07/2000US6144053 Semiconductor device having a capacitor with a high dielectric constant film
11/07/2000US6144052 Semiconductor device and its manufacture
11/07/2000US6144051 Semiconductor device having a metal-insulator-metal capacitor
11/07/2000US6144050 Electronic devices with strontium barrier film and process for making same
11/07/2000US6144049 Field effect transistor
11/07/2000US6144048 Heterojunction field effect transistor and method of fabricating the same
11/07/2000US6144047 Semiconductor device having impurity concentrations for preventing a parasitic channel
11/07/2000US6144042 Polysilicon thin film transistor
11/07/2000US6144041 A semiconductor with active region in which no grain boundary exists comprising a hydrogen or halogen element, nitrogen and carbon atoms, oxygen atoms to neutralize a point defect at specific densities, and metal for promoting crystallilztion
11/07/2000US6143992 Circuit board with terminals having a solder lead portion
11/07/2000US6143991 Bump electrode with adjacent pad and insulation for solder flow stopping
11/07/2000US6143981 Plastic integrated circuit package and method and leadframe for making the package
11/07/2000US6143855 Each silicon atom is bonded to at least three oxygen atoms and to either a hyrogen atom or organic substituent; no hydroxyl or alkoxy substituents; use as low dielectric film
11/07/2000US6143706 For cleaning substrates such as semiconductors; prevents substrate surface from being contaminated with metal impurities from the surface treatment composition and stably provides clean substrate surface
11/07/2000US6143705 Treating semiconductor surface with cleaning agent consisting of organic acid having and complexing agent other than organic acid having chelating ability to remove metallic contaminants on substrate surface without corroding metallized wirings
11/07/2000US6143673 Method for forming gap filling silicon oxide intermetal dielectric (IMD) layer formed employing ozone-tEOS
11/07/2000US6143672 Method of reducing metal voidings in 0.25 μm AL interconnect
11/07/2000US6143671 Semiconductor device manufacturing method
11/07/2000US6143670 Method to improve adhesion between low dielectric constant layer and silicon containing dielectric layer
11/07/2000US6143669 Method of growing gate oxides
11/07/2000US6143668 KLXX technology with integrated passivation process, probe geometry and probing process
11/07/2000US6143667 Method and apparatus for using photoemission to determine the endpoint of an etch process
11/07/2000US6143666 Plasma surface treatment method for forming patterned TEOS based silicon oxide layer with reliable via and interconnection formed therethrough
11/07/2000US6143665 Method of etching
11/07/2000US6143664 Method of planarizing a structure having an interpoly layer
11/07/2000US6143663 Employing deionized water and an abrasive surface to polish a semiconductor topography
11/07/2000US6143662 Chemical mechanical polishing composition and method of polishing a substrate
11/07/2000US6143661 Method of processing semiconductor device with laser
11/07/2000US6143660 Method of producing a contact between a metallizing layer and a semiconductor material
11/07/2000US6143659 Method for manufacturing aluminum metal interconnection layer by atomic layer deposition method
11/07/2000US6143658 Multilevel wiring structure and method of fabricating a multilevel wiring structure
11/07/2000US6143657 Selectively growing copper germanide compound as deposit on bottom of contact hole, forming barrier layer over copper germanide, forming copper plug thereover
11/07/2000US6143656 Chemical mechanical polishing copper filled damascene opening using slurry comprising alumina and oxalic acid
11/07/2000US6143655 Methods and structures for silver interconnections in integrated circuits
11/07/2000US6143654 Method of forming tungsten pattern for a semiconductor device
11/07/2000US6143653 Method of forming tungsten interconnect with tungsten oxidation to prevent tungsten loss
11/07/2000US6143652 Forming aluminum-copper alloy layer over semiconductor substrate, performing rapid thermal processing to remelt extracted copper into alloy bulk, forming photoresist layer over alloy layer, etching alloy layer to transfer pattern
11/07/2000US6143651 Method of manufacturing a semiconductor device with a multilayer wiring
11/07/2000US6143650 Semiconductor interconnect interface processing by pulse laser anneal
11/07/2000US6143649 Forming layer of conductive material in dielectric layer, forming layer of hard mask material onto portion thereof, etching hard mask material to expose portion of first layer, forming facets on hard mask layer, forming via in first layer
11/07/2000US6143648 Method for forming an integrated circuit
11/07/2000US6143647 Silicon-rich block copolymers to achieve unbalanced vias
11/07/2000US6143646 Dual in-laid integrated circuit structure with selectively positioned low-K dielectric isolation and method of formation
11/07/2000US6143645 Reduced temperature contact/via filling
11/07/2000US6143644 Method to prevent passivation from keyhole damage and resist extrusion
11/07/2000US6143643 Process for manufacture of integrated circuit device using organosilicate insulative matrices
11/07/2000US6143642 Programmable semiconductor structures and methods for making the same
11/07/2000US6143641 Structure and method for controlling copper diffusion and for utilizing low K materials for copper interconnects in integrated circuit structures
11/07/2000US6143640 Method of fabricating a stacked via in copper/polyimide beol
11/07/2000US6143639 Methods of forming electrically conductive interconnections and electrically interconnected substrates
11/07/2000US6143638 Passivation structure and its method of fabrication
11/07/2000US6143637 Process for production of semiconductor device and cleaning device used therein
11/07/2000US6143636 High density flash memory
11/07/2000US6143635 Field effect transistors with improved implants and method for making such transistors
11/07/2000US6143634 Semiconductor process with deuterium predominance at high temperature
11/07/2000US6143632 Deuterium doping for hot carrier reliability improvement
11/07/2000US6143631 Method for controlling the morphology of deposited silicon on a silicon dioxide substrate and semiconductor devices incorporating such deposited silicon
11/07/2000US6143630 Method of impurity gettering
11/07/2000US6143629 Process for producing semiconductor substrate
11/07/2000US6143628 Semiconductor substrate and method of manufacturing the same
11/07/2000US6143627 Locally oxidizing silicon substrates of semiconductor wafers to grow patterned regions of oxide without formation of bird's beak structures and without need for reflowing oxide
11/07/2000US6143626 Method of manufacturing a semiconductor device using a trench isolation technique
11/07/2000US6143625 Protective liner for isolation trench side walls and method
11/07/2000US6143624 Ion implanting impurities proximate trench edges to enhance silicon oxidation rate and increase thickness of resulting oxide at trench edges
11/07/2000US6143623 Method of forming a trench isolation for semiconductor device with lateral projections above substrate
11/07/2000US6143622 Method for forming alignment mark
11/07/2000US6143620 Semiconductor processing method of providing a roughened polysilicon film and a capacitor construction
11/07/2000US6143619 Method for manufacturing semiconductor device and semiconductor device manufacturing apparatus
11/07/2000US6143618 Applying in-situ high temperature anneal to wafer within chemical vapor deposition reactor immediately prior to deposition of silicon oxide
11/07/2000US6143617 Composite capacitor electrode for a DRAM cell
11/07/2000US6143616 Methods of forming coaxial integrated circuitry interconnect lines
11/07/2000US6143615 Method of forming a resistor
11/07/2000US6143614 Monolithic inductor
11/07/2000US6143613 Selective exclusion of silicide formation to make polysilicon resistors
11/07/2000US6143612 High voltage transistor with high gated diode breakdown, low body effect and low leakage
11/07/2000US6143611 Semiconductor processing methods, methods of forming electronic components, and transistors
11/07/2000US6143610 Method for fabricating high-density semiconductor read-only memory device
11/07/2000US6143609 Method for forming semiconductor memory device
11/07/2000US6143608 Producing gate oxide regions in periphery regions of semiconductor chips, wherein the gate oxide regions have improved electrical properties such as increased breakdown voltage and increased reliability
11/07/2000US6143607 Method for forming flash memory of ETOX-cell programmed by band-to-band tunneling induced substrate hot electron and read by gate induced drain leakage current
11/07/2000US6143606 Method for manufacturing split-gate flash memory cell
11/07/2000US6143605 Method for making a DRAM capacitor using a double layer of insitu doped polysilicon and undoped amorphous polysilicon with HSG polysilicon
11/07/2000US6143604 Method for fabricating small-size two-step contacts for word-line strapping on dynamic random access memory (DRAM)
11/07/2000US6143603 Method of manufacturing bottom electrode of a capacitor
11/07/2000US6143602 Methods of forming memory device storage capacitors using protruding contact plugs
11/07/2000US6143601 Method of fabricating DRAM
11/07/2000US6143600 Method of fabricating a semiconductor memory device having bit line directly held in contact through contact with impurity region in self-aligned manner
11/07/2000US6143599 Method for manufacturing memory cell with trench capacitor
11/07/2000US6143598 Method of fabrication of low leakage capacitor
11/07/2000US6143597 Method of manufacturing capacitor included in semiconductor device and the capacitor thereof
11/07/2000US6143596 Planarization for interlayer dielectric
11/07/2000US6143595 Method for forming buried contact
11/07/2000US6143593 Elevated channel MOSFET
11/07/2000US6143592 MOS semiconductor device and method of fabricating the same
11/07/2000US6143591 Methods of forming SOI insulator layers, methods of forming transistor devices, and semiconductor devices and assemblies
11/07/2000US6143582 High density electronic circuit modules
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