Patents
Sitemap › H01 - Basic electric elements › H01L - Semiconductor devices; Electric solid state devices not otherwise provided for › H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
Patents for H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof (658,974)
10/2000
10/24/2000US6137740 Semiconductor memory device configured with I/O separation
10/24/2000US6137728 Nonvolatile reprogrammable interconnect cell with programmable buried source/drain in sense transistor
10/24/2000US6137718 Method for operating a non-volatile memory cell arrangement
10/24/2000US6137713 Semiconductor storage device
10/24/2000US6137664 Well resistor for ESD protection of CMOS circuits
10/24/2000US6137633 Laser irradiating apparatus and laser irradiating method
10/24/2000US6137574 Systems and methods for characterizing and correcting cyclic errors in distance measuring and dispersion interferometry
10/24/2000US6137570 System and method for analyzing topological features on a surface
10/24/2000US6137562 Substrate adjuster, substrate holder and substrate holding method
10/24/2000US6137561 Exposure apparatus for aligning photosensitive substrate with image plane of a projection optical system
10/24/2000US6137551 Liquid crystal display, thin film transistor array, and method of fabricating same with storage capacitor providing high aspect ratio
10/24/2000US6137347 Mid supply reference generator
10/24/2000US6137345 Semiconductor integrated circuit including a boosted potential generating circuit
10/24/2000US6137330 Integrated circuit including functional blocks controlled by common synchronizing control transistors
10/24/2000US6137316 Integrated circuit with improved off chip drivers
10/24/2000US6137302 Low-current probe card with reduced triboelectric current generating cables
10/24/2000US6137297 Electronic test probe interface assembly and method of manufacture
10/24/2000US6137296 Probe card for testing semiconductor devices
10/24/2000US6137295 Method of detecting defect of integrated circuit and apparatus thereof
10/24/2000US6137224 Electronic device encapsulated directly on a substrate
10/24/2000US6137186 Semiconductor wafer, wafer alignment patterns and method of forming wafer alignment patterns
10/24/2000US6137185 Electrode structure of a wiring substrate of semiconductor device having expanded pitch
10/24/2000US6137184 Flip-chip type semiconductor device having recessed-protruded electrodes in press-fit contact
10/24/2000US6137183 Flip chip mounting method and semiconductor apparatus manufactured by the method
10/24/2000US6137182 Method of reducing via and contact dimensions beyond photolithography equipment limits
10/24/2000US6137180 Low cost DRAM metallization
10/24/2000US6137179 Method for fabricating capacitor-over-bit line (COB) dynamic random access memory (DRAM) using tungsten landing plug contacts and TI/TIN bit lines
10/24/2000US6137178 Semiconductor metalization system and method
10/24/2000US6137177 CMOS semiconductor device
10/24/2000US6137176 Semiconductor device and method of fabricating the same
10/24/2000US6137175 Semiconductor device with multi-layer wiring
10/24/2000US6137172 Method and device for positioning and retaining micro-building-blocks
10/24/2000US6137166 Semiconductor device
10/24/2000US6137158 Leadframe and leadframe assembly for parallel optical computer link
10/24/2000US6137152 Planarized deep-shallow trench isolation for CMOS/bipolar devices
10/24/2000US6137149 Semiconductor device having raised source-drains and method of fabricating the same
10/24/2000US6137148 NMOS transistor
10/24/2000US6137147 Bipolar transistor and semiconductor integrated circuit device
10/24/2000US6137146 Bipolar transistor and method of forming BiCMOS circuitry
10/24/2000US6137145 Semiconductor topography including integrated circuit gate conductors incorporating dual layers of polysilicon
10/24/2000US6137142 MOS device structure and method for reducing PN junction leakage
10/24/2000US6137141 MOS device and fabrication method
10/24/2000US6137139 Low voltage dual-well MOS device having high ruggedness, low on-resistance, and improved body diode reverse recovery
10/24/2000US6137137 CMOS semiconductor device comprising graded N-LDD junctions with increased HCI lifetime
10/24/2000US6137136 Power semiconductor device
10/24/2000US6137135 Semiconductor device and method of fabricating the same
10/24/2000US6137134 Semiconductor memory device
10/24/2000US6137133 Programmable non-volatile memory cell and method of forming a non-volatile memory cell
10/24/2000US6137132 High density buried bit line flash EEPROM memory cell with a shallow trench floating gate
10/24/2000US6137131 Dram cell with a multiple mushroom-shaped capacitor
10/24/2000US6137130 Capacitor over bit line structure using a straight bit line shape
10/24/2000US6137129 High performance direct coupled FET memory cell
10/24/2000US6137128 Self-isolated and self-aligned 4F-square vertical fet-trench dram cells
10/24/2000US6137126 Method to reduce gate-to-local interconnect capacitance using a low dielectric constant material for LDD spacer
10/24/2000US6137125 Two layer hermetic-like coating for on-wafer encapsulatuon of GaAs MMIC's having flip-chip bonding capabilities
10/24/2000US6137119 Apparatus for isolating a conductive region from a substrate during manufacture of an integrated circuit and connecting the conductive region to the substrate after manufacture
10/24/2000US6137113 Electron beam exposure method and apparatus
10/24/2000US6137112 Time of flight energy measurement apparatus for an ion beam implanter
10/24/2000US6137105 Multiple parallel source scanning device
10/24/2000US6137063 Electrical interconnections
10/24/2000US6137018 Removing ionic impurities contained in waste isopropyl alcohol; removing metallic impurities fromn waste; removing water; removing particles; returning isopropyl alcohol to storage for future use
10/24/2000US6136767 Dilute composition cleaning method
10/24/2000US6136729 Low heating the semiconductor wafer with the formed dielectric layer in the absence of oxygen, slowly increasing the heating temperature for the dielectric layer to repel wet etch chemicals and minimize the formation of holes defect
10/24/2000US6136728 Annealing the dielectric layer in a water vapor atmosphere to improve the electrical properties
10/24/2000US6136727 Preheating a silicon carbide substrate in an atmosphere comprising hydrogen, then oxidation to form silicon dioxide dielectric layer
10/24/2000US6136726 Method of forming interlayer film by altering fluidity of deposited layers
10/24/2000US6136725 Method for chemical vapor deposition of a material on a substrate
10/24/2000US6136724 Multiple stage wet processing chamber
10/24/2000US6136723 Dry etching process and a fabrication process of a semiconductor device using such a dry etching process
10/24/2000US6136722 Selectively etching silicon dioxide film through a window of masking film using a fluorocarbon-based etching gas and forming a fluorocarbon polymer film on the masking film
10/24/2000US6136721 Method and apparatus for dry etching
10/24/2000US6136720 Plasma processing tools dual-source plasma etchers, dual-source plasma etching methods, and methods of forming planar coil dual-source plasma etchers
10/24/2000US6136719 Method and arrangement for fabricating a semiconductor device
10/24/2000US6136718 Method for manufacturing a semiconductor wafer using a threadless corrosion-preventing gas ring
10/24/2000US6136717 Method for producing a via hole to a doped region
10/24/2000US6136716 Method for manufacturing a self-aligned stacked storage node DRAM cell
10/24/2000US6136714 A two step polishing process comprising a metal removal-enhancing amount of at least one chelating agent aminocarboxylic acid
10/24/2000US6136713 Method for forming a shallow trench isolation structure
10/24/2000US6136712 Method and apparatus for improving accuracy of plasma etching process
10/24/2000US6136711 Polishing composition including an inhibitor of tungsten etching
10/24/2000US6136709 Metal line deposition process
10/24/2000US6136708 Preventing the diffusion of contaminants by forming a barrier film on a back surface of a semiconductor substrate; significant reduction in production steps
10/24/2000US6136707 Seed layers for interconnects and methods for fabricating such seed layers
10/24/2000US6136705 Depositing a silicon layer above the silicon substrate, covering a cobalt layer and then a titanium capping layer, reacting cobalt from the cobalt layer with silicon from silicon layer and from silicon substrate
10/24/2000US6136704 Sputtering a crystalline platinum oxide layer over the substrate, chemically reducing the crystalline platinum oxide layer to form the platinum film electrodes
10/24/2000US6136703 Methods for forming phosphorus- and/or boron-containing silica layers on substrates
10/24/2000US6136702 Thin film transistors
10/24/2000US6136701 Contact structure for semiconductor device and the manufacturing method thereof
10/24/2000US6136700 Selectively etching portions of an insulating layer formed overlying the stopping layer to form a contact region
10/24/2000US6136699 Heating to change the formed refractory metal silicide layer from a first phase structure into a second phase structure
10/24/2000US6136698 Method of increasing contact area of a contact window
10/24/2000US6136697 Void-free and volcano-free tungsten-plug for ULSI interconnection
10/24/2000US6136696 Method of forming a semiconductor device with a conductor plug including five dielectric layers, the fourth dielectric layer forming sidewall spacers
10/24/2000US6136695 Method for fabricating a self-aligned contact
10/24/2000US6136694 Method for forming via hole
10/24/2000US6136693 Method for planarized interconnect vias using electroless plating and CMP
10/24/2000US6136692 Reducing contact resistance between the titanium nitride plug and the polysilicon electrode
10/24/2000US6136691 Vapor depositing a titanium nitride layer as a barrier layer; in situ plasma sputtering and eliminate any fluorine contamination
10/24/2000US6136690 In situ plasma pre-deposition wafer treatment in chemical vapor deposition technology for semiconductor integrated circuit applications
10/24/2000US6136689 Method of forming a micro solder ball for use in C4 bonding process
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