Patents
Sitemap › H01 - Basic electric elements › H01L - Semiconductor devices; Electric solid state devices not otherwise provided for › H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
Patents for H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof (658,974)
10/2000
10/31/2000US6140242 Method of forming an isolation trench in a semiconductor device including annealing at an increased temperature
10/31/2000US6140241 High aspect ratio contact/via openings is described. the method is designed to give good coverage and gap filling.
10/31/2000US6140240 Method for eliminating CMP induced microscratches
10/31/2000US6140239 Abrasion of cu metallization is reduced and residual slurry particulate removal facilitated by employing slurry containing dispersion of iron oxide particles having high solubility in dilute acids.
10/31/2000US6140238 Self-aligned copper interconnect structure and method of manufacturing same
10/31/2000US6140237 Damascene process for forming coplanar top surface of copper connector isolated by barrier layers in an insulating layer
10/31/2000US6140236 High throughput A1-Cu thin film sputtering process on small contact via for manufacturable beol wiring
10/31/2000US6140235 High pressure copper fill at low temperature
10/31/2000US6140234 Method to selectively fill recesses with conductive metal
10/31/2000US6140233 Method of manufacturing semiconductor devices, etching compositions for manufacturing semiconductor devices, and semiconductor devices thereby
10/31/2000US6140232 Method for reducing silicide resistance
10/31/2000US6140231 Tantalum nitride
10/31/2000US6140230 Methods of forming metal nitride and silicide structures
10/31/2000US6140229 Semiconductor apparatus and method of producing same
10/31/2000US6140228 Low temperature metallization process
10/31/2000US6140227 Method of fabricating a glue layer of contact/via
10/31/2000US6140226 Dual damascene processing for semiconductor chip interconnects
10/31/2000US6140225 Method of manufacturing semiconductor device having multilayer wiring
10/31/2000US6140224 Method of forming a tungsten plug
10/31/2000US6140223 Methods of forming contacts for integrated circuits using chemical vapor deposition and physical vapor deposition
10/31/2000US6140222 To provide isolation between electrical conductors, phosphorous doped dielectric prevents sodium from becoming mobile under the influence of subsequently applied electric fields.
10/31/2000US6140221 Method for forming vias through porous dielectric material and devices formed thereby
10/31/2000US6140220 Relative selectivity of the etch between silicon oxide and silicon nitride is carefully adjusted, patterned layer imbedded on and in another layer such that the top surfaces of the two layers are coplanar.
10/31/2000US6140219 Method of forming contact openings
10/31/2000US6140218 Method for fabricating a T-shaped hard mask/conductor profile to improve self-aligned contact isolation
10/31/2000US6140217 Technique for extending the limits of photolithography
10/31/2000US6140216 Post etch silicide formation using dielectric etchback after global planarization
10/31/2000US6140215 Method and apparatus for low temperature deposition of CVD and PECVD films
10/31/2000US6140214 Semiconductor processing methods, semiconductor processing methods of forming diodes, and semiconductor processing methods of forming schottky diodes
10/31/2000US6140213 Semiconductor wafer and method of manufacturing same
10/31/2000US6140211 Method for recycling wafers used for quality assurance testing of integrated circuit fabrication equipment
10/31/2000US6140210 Method of fabricating an SOI wafer and SOI wafer fabricated thereby
10/31/2000US6140209 Process for forming an SOI substrate
10/31/2000US6140208 Shallow trench isolation (STI) with bilayer of oxide-nitride for VLSI applications
10/31/2000US6140207 Method of isolating semiconductor devices
10/31/2000US6140206 Method to form shallow trench isolation structures
10/31/2000US6140205 Method of forming retrograde well in bonded waffers
10/31/2000US6140204 Process for producing a semiconductor device having hemispherical grains (HSG)
10/31/2000US6140203 Capacitor constructions and semiconductor processing method of forming capacitor constructions
10/31/2000US6140202 Method of fabricating double-cylinder capacitor
10/31/2000US6140201 Method for fabricating a cylinder capacitor
10/31/2000US6140200 Methods of forming void regions dielectric regions and capacitor constructions
10/31/2000US6140199 Method and arrangement of a buried capacitor, and a buried capacitor arranged according to said method
10/31/2000US6140198 Method of fabricating load resistor
10/31/2000US6140197 Method of making spiral-type RF inductors having a high quality factor (Q)
10/31/2000US6140196 Method of fabricating high power bipolar junction transistor
10/31/2000US6140195 Method for fabricating a lateral collector structure on a buried oxide layer
10/31/2000US6140194 Method relating to the manufacture of a semiconductor component
10/31/2000US6140193 Method for forming a high-voltage semiconductor device with trench structure
10/31/2000US6140192 Method for fabricating semiconductor device
10/31/2000US6140191 Method of making high performance MOSFET with integrated simultaneous formation of source/drain and gate regions
10/31/2000US6140190 Method and structure for elevated source/drain with polished gate electrode insulated gate field effect transistors
10/31/2000US6140189 Method for fabricating a LOCOS MOS device for ESD protection
10/31/2000US6140187 Process for forming metal oxide semiconductors including an in situ furnace gate stack with varying silicon nitride deposition rate
10/31/2000US6140186 Method of forming asymmetrically doped source/drain regions
10/31/2000US6140185 Method of manufacturing semiconductor device
10/31/2000US6140183 Method of fabricating semiconductor device
10/31/2000US6140182 Nonvolatile memory with self-aligned floating gate and fabrication process
10/31/2000US6140180 Method of fabricating storage capacitor for dynamic random-access memory
10/31/2000US6140179 Method of forming a crown capacitor for a DRAM cell
10/31/2000US6140178 Method to manufacture a capacitor with crown-shape using edge contact exposure
10/31/2000US6140177 Process of forming a semiconductor capacitor including forming a hemispherical grain statistical mask with silicon and germanium
10/31/2000US6140176 Method and fabricating a self-aligned node contact window
10/31/2000US6140175 Self-aligned deep trench DRAM array device
10/31/2000US6140174 Methods of forming wiring layers on integrated circuits including regions of high and low topography
10/31/2000US6140173 Method of manufacturing a semiconductor device comprising a ferroelectric memory element
10/31/2000US6140172 Conductive electrical contacts, capacitors, DRAMs, and integrated circuitry, and methods of forming conductive electrical contacts, capacitors, DRAMs and integrated circuitry
10/31/2000US6140171 FET device containing a conducting sidewall spacer for local interconnect and method for its fabrication
10/31/2000US6140170 Manufacture of complementary MOS and bipolar integrated circuits
10/31/2000US6140169 Method for manufacturing field effect transistor
10/31/2000US6140168 Method of fabricating self-aligned contact window
10/31/2000US6140167 High performance MOSFET and method of forming the same using silicidation and junction implantation prior to gate formation
10/31/2000US6140166 Method for manufacturing semiconductor and method for manufacturing semiconductor device
10/31/2000US6140165 Semiconductor device forming method
10/31/2000US6140164 Method of manufacturing a semiconductor device
10/31/2000US6140163 Method and apparatus for upper level substrate isolation integrated with bulk silicon
10/31/2000US6140162 Reduction of masking and doping steps in a method of fabricating a liquid crystal display
10/31/2000US6140161 Semiconductor integrated circuit device and method for making the same
10/31/2000US6140160 Method for fabricating a simplified CMOS polysilicon thin film transistor and resulting structure
10/31/2000US6140159 Method for activating an ohmic layer for a thin film transistor
10/31/2000US6140158 Method of manufacturing thin film transistor-liquid crystal display
10/31/2000US6140157 Memory device using movement of protons
10/31/2000US6140156 Fabrication method of isolation structure photodiode
10/31/2000US6140155 Method of manufacturing semiconductor device using dry photoresist film
10/31/2000US6140153 Lead frame, the manufacturing method, semiconductor device and the manufacturing method
10/31/2000US6140151 Semiconductor wafer processing method
10/31/2000US6140149 Device and method for stacking wire-bonded integrated circuit dice on flip-chip bonded integrated circuit dice
10/31/2000US6140148 Method of making a contact to a diamond
10/31/2000US6140147 Method for driving solid-state imaging device
10/31/2000US6140140 Method for detecting process sensitivity to integrated circuit layout by compound processing
10/31/2000US6140027 Photoresist remover composition
10/31/2000US6140024 Low temperature process of forming an opening in silicon wafers with oxide layer, exposure to nitrogen ion to form nitride, forming photoresists then etching and removing photoresists
10/31/2000US6140021 Charged particle beam transfer method
10/31/2000US6140020 Method for manufacturing a semiconductor wafer using a mask that has several regions with different scattering ability
10/31/2000US6140010 Polymer with crosslinker, photoacid generator which generates acid in response to light with acrylic ester with terminal acid group
10/31/2000US6140009 Heat exchangers for electroluminescent device formed by positioning the transfer layer on receptor substrate and heat exchanging
10/31/2000US6139995 Method of manufacturing schottky gate transistor utilizing alignment techniques with multiple photoresist layers
10/31/2000US6139993 Substrate with patterns and shields, irradiation of body with ion beam to remove part of body from substrate and radiation body and light transmission area for removal of body of material from substrate
10/31/2000US6139992 Computers
10/31/2000US6139983 Containing a fluoride of at least one element selected from the group consisting of rare earth elements and alkaline earth elements.
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